Hierarchical DFT with Combinational Scan Compression, Partition Chain and RPCT

Abstract

Modular and hierarchical based test architecture are the two of the most common testing techniques used in complex SoC designs. However, modular test architectures uses an expensive (in terms of silicon area) test wrapper around each block. On the other hand hierarchical test architecture requires additional effort at block level to isolate each block from surrounding blocks and a TAM to perform scan compression. In this paper, we analyze the limitations of the modular test architecture. Based on the analysis, we propose a test plan for hierarchical test architecture by integrating partition chain, combinational scan compression and (RPCT) reduced pin count test. Experimental results show that approximately 50% of DFT area can be reduced using the partition chain as compared to standard test wrapper. It also demonstrates the feasibility of the proposed test plan using a commercial ATPG tool. I.

A Case Study on Implementing Compressed DFT Architecture

“…The standard wrapper cells can be rather large and for big cores with large number of ports on the boundary, the silicon area and the performance penalty could be prohibitive. To work around these problems, techniques have been presented on designing the hierarchical test solutions with unwrapped cores [8] [9], with a mix of wrapped and unwrapped cores [10] and using a mix of wrappers and functional flops of the design [11]- [13].…”

“…However, this may result in a large functional register based isolation boundary and will force a large amount of core internal logic to be tested with the surrounding logic. The work presented in [13] uses the block isolation technique presented in [11] and proposes a hierarchical test architecture using shared wrapper chains, scan compression and reduced pin-count test (RPCT).…”

“…Hierarchical DFT methods with compression and wrappers has been studied in detail in [13]. In this paper, shared wrapper chain based TAM [11] [19] and the compression solution called Illinois Scan Architecture (ILS) [21] for the input side and X-compactor [23] method for the output side have been used for the analysis.…”