Hierarchical congregated ant system for bottom-up VLSI placements

Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

“…It is a common technique where clusters are placed into a partition, and then the partition is treated as a new cluster [7]. Also, assume two child clusters with the dimensions of w 1 , h 1 , w 2 and h 2 as their heights and widths, respectively, where the widths of child clusters and child partitions are the same, and h 1 and h 2 are maximally equal to h. By summing the areas of these two child partitions, which are Q 1 and Q 2 , respectively, we have the area of the cluster Q = Q 1 + Q 2 , where Q 1 ≤ Q, and Q 2 ≤ Q.…”

“…In bottom-up clustering technique, the dimension of the partition will be shrunk until all the child clusters are just sufficiently being fitted in [7]. Thus, it is distinctly evidenced that the relative whitespace of a partition with two child partitions is a convex combination of its own child partitions' relative whitespaces.…”

“…The normalized value is defined as the ratio of the results of the other algorithms to the CABF results [7]. The normalized value is defined as the ratio of the results of the other algorithms to the CABF results [7].…”

“…Hence, floorplanning [1][2][3][4][5][6][7] is a crucial step in VLSI circuit design [8] as it determines the quality of the deep submicron chip quality, manufacturing cost and the time-to-market. Hence, floorplanning [1][2][3][4][5][6][7] is a crucial step in VLSI circuit design [8] as it determines the quality of the deep submicron chip quality, manufacturing cost and the time-to-market.…”

“…Since floorplan framework has a direct impact on the floorplanning results [7], different framework approaches are proposed to handle the floorplanning problems, depending on their scale and difficulties. Since floorplan framework has a direct impact on the floorplanning results [7], different framework approaches are proposed to handle the floorplanning problems, depending on their scale and difficulties.…”