Variable-Order Ant System for VLSI multiobjective floorplanning

Hoo, Chyi-Shiang; Kanesan, Jeevan; Ganapathy, Velappa; Ramiah, Harikrishnan

doi:10.1016/j.asoc.2013.02.011

Cited by 25 publications

(4 citation statements)

References 29 publications

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“…CL is a sequence-based representation used to represent the initial floorplan [9]. In MCL based approach, the floorplan layouts can be formed using corner list.…”

Section: Modified Corner List Representationmentioning

confidence: 99%

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Optimization of Thermal Aware VLSI Non-Slicing Floorplanning Using Hybrid Particle Swarm Optimization Algorithm-Harmony Search Algorithm

Paramasivam¹,

Athappan²,

Natrajan³

et al. 2016

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Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimating the positions and shapes of the modules. A high packing density, small feature size and high clock frequency make the Integrated Circuit (IC) to dissipate large amount of heat. So, in this paper, a methodology is presented to distribute the temperature of the module on the layout while simultaneously optimizing the total area and wirelength by using a hybrid Particle Swarm Optimization-Harmony Search (HPSOHS) algorithm. This hybrid algorithm employs diversification technique (PSO) to obtain global optima and intensification strategy (HS) to achieve the best solution at the local level and Modified Corner List algorithm (MCL) for floorplan representation. A thermal modelling tool called hotspot tool is integrated with the proposed algorithm to obtain the temperature at the block level. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The results obtained are compared with the solutions derived from other stochastic algorithms and the proposed algorithm provides better solution.

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“…CL is a sequence-based representation used to represent the initial floorplan [9]. In MCL based approach, the floorplan layouts can be formed using corner list.…”

Section: Modified Corner List Representationmentioning

confidence: 99%

“…To represent non-slicing floorplan, different representations are proposed: tree-based approach [5] sequence based approach [4] [8], corner list approach [6] [9] and transitive closure graph [10]. From the literature, corner list method shows better representation in terms of search space O((n!)…”

Section: Introductionmentioning

confidence: 99%

Optimization of Thermal Aware VLSI Non-Slicing Floorplanning Using Hybrid Particle Swarm Optimization Algorithm-Harmony Search Algorithm

Paramasivam¹,

Athappan²,

Natrajan³

et al. 2016

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show abstract

“…In line with this, modern VLSI design using fixed outline design, as proposed by Adya and Markov [1], has become more challenging. For the case of area minimisation, fixed outline floorplanning is much more difficult than classical outline‐free floorplanning [2, 3]. In this paper, our main objective is to optimise the fixed‐outline floorplan's wirelength while addressing the constraint of fixed‐outline.…”

Section: Introductionmentioning

confidence: 99%

Enumeration technique in very large‐scale integration fixed‐outline floorplanning

Hoo

Kanesan

Ramiah

2014

IET Circuits, Devices & Systems

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Even though enumeration is a common technique adapted in very large-scale integration (VLSI) floorplanning, its impact in terms of wirelength, whitespace, as well as runtime on the floorplanning has never been investigated comprehensively. In this study, enumerative floorplanner (EFP) is proposed here by using enumeration. The impact of the maximum enumeration order on VLSI floorplan layout is investigated and the tradeoff relationship with the wirelength, area and runtime is analysed as well. In EFP, dynamic programming enumerative clustering (DEC) technique is employed to reduce the worst-case time complexity and runtime. DEC also introduces the same number of possible permutations of modules while reducing the redundancy created in enumerative clustering (EC) without the usage of dynamic programming. A straightforward cost function is adapted to assist DEC to select the best cluster permutation, and a rigorous local refinement is proposed to compensate the EC's impact on the floorplan wirelength. Experimental results show that EFP is a high performance floorplanner when compared to existing methods in terms of robustness, scalability and stability.

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“…Hence, floorplanning [1][2][3][4][5][6][7] is a crucial step in VLSI circuit design [8] as it determines the quality of the deep submicron chip quality, manufacturing cost and the time-to-market. Although there are several circuit design objectives to be considered during floorplanning, such as area minimization, wirelength optimization [9], delay reduction [10,11], thermal stability [12][13][14], clock tree synthesis [15] or any combination of these objectives [16][17][18], the basic objective of floorplanning is to minimize the area of the VLSI chip.…”

Section: Introductionmentioning

confidence: 99%

Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

Hoo

Kanesan

Ramiah

2013

Circuit Theory & Apps

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From the industrial perspective, floorplanning is a crucial step in the VLSI physical design process as its efficiency determines the quality and the time-to-market of the product. A new perturbation method, called Cull-and-Aggregate Bottom-up Floorplanner (CABF), which consists of culling and aggregating stages, is developed to perform variable-order automated floorplanning for VLSI. CABF will generate VLSI floorplan layout by calculating the modules' dimensions' differences (hard module floorplanning problems) and the modules' areas' differences (soft module floorplanning problems). Through mathematical derivation, the hard modules floorplanning area minimization cost function (two-dimensional) during culling stage is proven that a dimensional reduction can be carried out to be the difference-based cost function (one-dimensional) which simplifies the computation. During the culling stage, CABF employs linear ordering method to select and determine the order of modules where this linear runtime complexity property allows CABF to cull the modules faster. The aggregating stage of CABF will reduce the subsequent search space of this floorplanner, and the variable order aggregation enables CABF to search for the best near-optimal solution. Based on Gigascale Systems Research Center and Microelectronics Center of North Carolina circuit benchmarks, CABF gives better optimal solutions and faster runtimes for floorplanning problems involving 9 to 600 modules. This has established that CABF is performing well in respect of reliability and scalability. Besides, CABF shows its potential to be implemented in VLSI physical design as the runtime of CABF is faster with a near-optimal outcome as compared to the other existing algorithms.

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Variable-Order Ant System for VLSI multiobjective floorplanning

Cited by 25 publications

References 29 publications

Optimization of Thermal Aware VLSI Non-Slicing Floorplanning Using Hybrid Particle Swarm Optimization Algorithm-Harmony Search Algorithm

Optimization of Thermal Aware VLSI Non-Slicing Floorplanning Using Hybrid Particle Swarm Optimization Algorithm-Harmony Search Algorithm

Enumeration technique in very large‐scale integration fixed‐outline floorplanning

Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

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