Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation

Mark, Cindy; Chin, Scott Y. L.; Shannon, Lesley; Wilton, Steven J. E.

doi:10.1145/2331147.2331152

Cited by 4 publications

(2 citation statements)

References 15 publications

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“…Let us arrange ( 9) and (10) in the form of a matrix. For a device whose coordinate vector is P, after an up-and-down mirror operation, the calculation formula for its coordinate vector P ud is…”

Section: Addressing Ports After Mirror Operationmentioning

confidence: 99%

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From Netlist to Manufacturable Layout: An Auto-Layout Algorithm Optimized for Radio Frequency Integrated Circuits

et al. 2023

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Layout stitching is a repetitive and tedious task of the radio frequency integrated circuit (RFIC) design process. While academic research on layout splicing algorithms mainly focuses on analog and digital circuits, there is still a lack of well-developed algorithms for RFICs. An RFIC system usually has a symmetrical layout, such as transmitter and receiver components, low-noise amplifier (LNA), an SPDT switch, etc. This paper aims to address this gap by proposing an automated procedure for the layout of RFICs by relying on the basic device/PCell structure based on the interconnection among circuit topologies. This approach makes the in-series generation of layouts and automatic splicing based on circuit logic possible, resulting in superior stitching performance compared with related modules in Advanced Design System. To demonstrate the physical application possibilities, we implemented our algorithm on an LNA and a switch circuit.

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Section: Addressing Ports After Mirror Operationmentioning

confidence: 99%

“…This method can be used with limited information, based on research on the reliability prediction of combinational circuits [9]. Cindy et al describe a random circuit generator used in FPGA architecture research [10]. The generated circuits form a hierarchy of interconnected modules.…”

Section: Introductionmentioning

confidence: 99%

From Netlist to Manufacturable Layout: An Auto-Layout Algorithm Optimized for Radio Frequency Integrated Circuits

et al. 2023

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Scalable Synthetic Circuit Generation using Geometry Embedding for CAD Tool Assessment

Lin

2022

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

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FPGA Architecture Exploration for DNN Acceleration

Leong

2022

ACM Trans. Reconfigurable Technol. Syst.

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Recent years have seen an explosion of machine learning applications implemented on Field-Programmable Gate Arrays (FPGAs) . FPGA vendors and researchers have responded by updating their fabrics to more efficiently implement machine learning accelerators, including innovations such as enhanced Digital Signal Processing (DSP) blocks and hardened systolic arrays. Evaluating architectural proposals is difficult, however, due to the lack of publicly available benchmark circuits. This paper addresses this problem by presenting an open-source benchmark circuit generator that creates realistic DNN-oriented circuits for use in FPGA architecture studies. Unlike previous generators, which create circuits that are agnostic of the underlying FPGA, our circuits explicitly instantiate embedded blocks, allowing for meaningful comparison of recent architectural proposals without the need for a complete inference computer-aided design (CAD) flow. Our circuits are compatible with the VTR CAD suite, allowing for architecture studies that investigate routing congestion and other low-level architectural implications. In addition to addressing the lack of machine learning benchmark circuits, the architecture exploration flow that we propose allows for a more comprehensive evaluation of FPGA architectures than traditional static benchmark suites. We demonstrate this through three case studies which illustrate how realistic benchmark circuits can be generated to target different heterogeneous FPGAs.

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Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation

Cited by 4 publications

References 15 publications

From Netlist to Manufacturable Layout: An Auto-Layout Algorithm Optimized for Radio Frequency Integrated Circuits

From Netlist to Manufacturable Layout: An Auto-Layout Algorithm Optimized for Radio Frequency Integrated Circuits

Scalable Synthetic Circuit Generation using Geometry Embedding for CAD Tool Assessment

FPGA Architecture Exploration for DNN Acceleration

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