High Efficiency Video Coding (HEVC) is the currently developing video coding standard beyond H.264/AVC. In this paper, a full pipelined 2-D IDCT/IDST VLSI architecture compatible with HEVC standard is presented for the first time. The proposed architecture supports adaptive block size IDCT from 4×4 to 32×32 pixels as well as IDST while keeping nearly 100% hardware utilization. Using SMIC 65 nm 1P9M technology, the synthesis results show that the architecture achieves the maximum work frequency at 480 MHz and the hardware cost is about 115.8 K Gates. Experimental results show that the proposed architecture is able to deal with realtime HEVC IDCT/IDST of 4 K×2 K (4096×2048)@30 fps video sequence at 171 MHz in average. In consequence, it offers a costeffective solution for the future UHDTV applications.