Heterogeneous parallel programming in Jade

Rinard,; Scales,; Lam, Hak‐Keung

doi:10.1109/superc.1992.236678

Cited by 12 publications

(8 citation statements)

References 16 publications

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“…These S-DSM are designed for a particular architecture and reasonably expect the same performance from the physical resources. Deploying S-DSM over heterogeneous systems has been studied in 1992 with Mermaid [15] and Jade [13] running on SPARC, DEC and DASH-based machines. With Mermaid, the authors focus on the problem of data conversion between processors.…”

Section: Related Workmentioning

confidence: 99%

Software-Distributed Shared Memory over Heterogeneous Micro-server Architecture

Cudennec

2018

Euro-Par 2017: Parallel Processing Workshops

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Nowadays, the design of computing architectures not only targets computing performances but also the energy power savings. Lowpower computing units, such as ARM and FPGA-based nodes, are now being integrated together with high-end processors and GPGPU accelerators into computing clusters. One example is the micro-server architecture that consists of a backbone onto which it is possible to plug computing nodes. These nodes can host high-end and low-end CPUs, GPUs, FPGAs and multi-purpose accelerators such as manycores, building up a real heterogeneous platform. In this context, there is no hardware to federate memories, and the programmability of such architectures suddenly relies on the developer experience to manage data location and task communications. The purpose of this paper is to evaluate the possibility of bringing back the convenient shared-memory programming model by deploying a software-distributed shared memory among heterogeneous computing nodes. We describe how we have built such a system over a message-passing runtime. Experimentations have been conducted using a parallel image processing application over an homogeneous cluster and an heterogeneous micro-server.

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Section: Related Workmentioning

confidence: 99%

Software-Distributed Shared Memory over Heterogeneous Micro-server Architecture

Cudennec

2018

Euro-Par 2017: Parallel Processing Workshops

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“…In particular, task-based dataflow programming models automate data dependency and solve the synchronization problem of static task management systems. Main examples of this class are StarSs family [3,4,28] (including OmpSs [6,8]), OoOJava [12,13], JADE [18,[29][30][31], and OpenMP 4.0 [25]. These models try to support dynamic task creation and scheduling with a simple programming model [4].…”

Section: Related Workmentioning

confidence: 99%

Design space exploration of hardware task superscalar architecture

Yazdanpanah

Alaei

2015

J Supercomput

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For current high performance computing systems, exploiting concurrency is a serious and important challenge. Recently, several dynamic software task management mechanisms have been proposed. In particular, task-based dataflow programming models which benefit from dataflow principles to improve task-level parallelism and overcome the limitations of static task management systems. However, these programming models rely on software-based dependency analysis, which are performed inherently slowly; and this limits their scalability specially when there is fine-grained task granularity and a large amount of tasks. Moreover, task scheduling in software introduces overheads, and so becomes increasingly inefficient with the number of cores. In contrast, a hardware scheduling solution, like Task SuperScalar (TSS), can achieve greater values of speed-up because a hardware task scheduler requires fewer cycles than the software version to dispatch a task. TSS combines the effectiveness of Out-of-Order processors together with the task abstraction. It has been implemented in software with limited parallelism and high memory consumption due to the nature of the software implementation. Hardware Task Superscalar (HTSS) is proposed to solve these drawbacks. HTSS is designed to be integrated in a future high performance computer with the ability to exploit fine-grained task parallelism. In this article, a deep latency and design space exploration of HTSS is described. For design space exploration, we have designed a full cycle-accurate simulator of HTSS, called SimTSS. The simulator has been tuned based on latency exploration of HTSS components resulted from VHDL description of each component. As the result of this exploration, we have found the number of components and memory capacity of HTSS for HPC systems. B Fahimeh Yazdanpanah

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“…The inspector/executor approach dynamically analyzes the values in index arrays to automatically parallelize computations that access irregular meshes [Leung and Zahorjan 1993;Saltz et al 1991]. The Jade implementation dynamically analyzes how tasks access data to exploit the concurrency in coarse-grain parallel programs [Rinard et al 1992]. Speculative approaches optimistically execute loops in parallel, rolling back the computation if the parallel execution violates the data dependences [Rauchwerger and Padua 1995].…”

Section: Run-time Analysis and Speculative Executionmentioning

confidence: 99%

Eliminating synchronization overhead in automatically parallelized programs using dynamic feedback

Diniz

Rinard

1999

ACM Trans. Comput. Syst.

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This article presents dynamic feedback, a technique that enables computations to adapt dynamically to different execution environments. A compiler that uses dynamic feedback produces several different versions of the same source code; each version uses a different optimization policy. The generated code alternately performs sampling phases and production phases. Each sampling phase measures the overhead of each version in the current environment. Each production phase uses the version with the least overhead in the previous sampling phase. The computation periodically resamples to adjust dynamically to changes in the environment.We have implemented dynamic feedback in the context of a parallelizing compiler for object-based programs. The generated code uses dynamic feedback to automatically choose the best synchronization optimization policy. Our experimental results show that the synchronization optimization policy has a significant impact on the overall performance of the computation, that the best policy varies from program to program, that the compiler is unable to statically choose the best policy, and that dynamic feedback enables the generated code to exhibit performance that is comparable to that of code that has been manually tuned to use the best policy. We have also performed a theoretical analysis which provides, under certain assumptions, a guaranteed optimality bound for dynamic feedback relative to a hypothetical (and unrealizable) optimal algorithm that uses the best policy at every point during the execution.

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Heterogeneous parallel programming in Jade

Cited by 12 publications

References 16 publications

Software-Distributed Shared Memory over Heterogeneous Micro-server Architecture

Software-Distributed Shared Memory over Heterogeneous Micro-server Architecture

Design space exploration of hardware task superscalar architecture

Eliminating synchronization overhead in automatically parallelized programs using dynamic feedback

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