Heterogeneous modeling and simulation of embedded systems in El Greco

Buck,; Vaidyanathan,

doi:10.1109/hsc.2000.843723

Cited by 18 publications

(23 citation statements)

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“…EC is currently used to generate simulation code in CoCentric System Studio (described under an earlier name by Buck and Vaidyanathan [23]), an environment that allows designers to specify systems using a mixture of dataflow graphs and hierarchical finite-state machines. To compile a simulation, System Studio translates control behavior into IC programs, EC compiles them into C, and the result is linked code generated by System Studio for the dataflow portion.…”

Section: Discussionmentioning

confidence: 99%

An Esterel compiler for large control-dominated systems

Edwards

2002

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Embedded hard real-time software systems often need fine-grained parallelism and precise control of timing, things typical real-time operating systems do not provide. The Esterel language has both, but compiling large Esterel programs has been challenging, producing either needlessly slow or large code. This paper presents the first Esterel compiler able to compile large Esterel programs into fast, small code. By choosing a concurrent control-flow graph (CCFG) as its intermediate representation, it preserves many of the control constructs to produce code that can be 100 times faster and half the size than code from other compilers with similar capacity. The primary contribution is an algorithm that generates efficient sequential code from a CCFG. While developed specifically for compiling Esterel, the algorithm could be used to compile other synchronous languages with fine-grained parallelism.

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Section: Discussionmentioning

confidence: 99%

An Esterel compiler for large control-dominated systems

Edwards

2002

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The modeling and simulation framework called El Greco [20] supports system specifications given as combinations of dataflow graphs and hierarchical FSMs. However, the framework is tailored for rapid simulation-based algorithm exploration.…”

Section: Introductionmentioning

confidence: 99%

“…However, the framework is tailored for rapid simulation-based algorithm exploration. Therefore, it is not clear from [20] how static analysis is performed in the presence of parameters.…”

Section: Introductionmentioning

confidence: 99%

Parameterized Dataflow Scenarios

Skelin

Geilen

Catthoor

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-A number of modeling approaches combining dataflow and finite-state machines (FSMs) have been proposed to capture applications that combine streaming data with finite control. FSM-based scenario-aware dataflow (FSM-SADF) is such an FSM/dataflow hybrid that occupies a sweet spot in the tradeoff between analyzability and expressiveness. However, the model suffers from compactness issues when the number of scenarios increases. This hampers its use in analysis of applications exposing high levels of data-dependent dynamics.In this article, we address this problem by combining parameterized dataflow with finite control of FSM-SADF. We refer to the generalization as FSM-based parameterized scenario-aware dataflow (FSM-πSADF). We introduce the formal semantics of the model, in terms of Max-plus algebra and in particular Maxplus automata. Thereafter, by leveraging the existing results of FSM-SADF, we propose a worst-case performance analysis framework for FSM-πSADF. We show that by using FSM-πSADF and its analysis framework, one can, unlike with FSM-SADF, compactly capture streaming applications exhibiting high levels of data-dependent dynamics in presence of finite control. Furthermore, we show that for practical models our analysis typically yields tighter bounds on worst-case performance indicators such as throughput and latency than the existing techniques based on conservative FSM-SADF modeling (if such modeling can be applied at all). We evaluate our approach on a realistic case-study from the multimedia domain.Index Terms-parameterized dataflow, finite-state machine, parameterized dataflow scenarios, synchronous dataflow, Maxplus algebra, worst-case performance.

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“…Synchronous dataflow (SDF) [1] has been used widely as an efficient model of computation for analyzing performance and resource requirements of DSP applications that are implemented on various target architectures (e.g., see [2], [3], [4], [5], [6]). …”

Section: Introduction and Related Workmentioning

confidence: 99%

Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs

Kee

Bhattacharyya

Kornerup

2010

2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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Abstract-When designing DSP applications for implementation on field programmable gate arrays (FPGAs), it is often important to minimize consumption of limited FPGA resources while satisfying real-time performance constraints. In this paper, we develop efficient techniques to determine dataflow graph buffer sizes that guarantee throughput-optimal execution when mapping synchronous dataflow (SDF) representations of DSP applications onto FPGAs. Our techniques are based on a novel two-actor SDF graph Model (TASM), which efficiently captures the behavior and costs associated with SDF graph edges (flowgraph connections). With our proposed techniques, designers can automatically generate upper bounds on SDF graph buffer distributions that realize maximum achievable throughput performance for the corresponding applications. Furthermore, our proposed techinque is characterized by low polynomial time complexity, which is useful for rapid prototyping in DSP system design.

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Heterogeneous modeling and simulation of embedded systems in El Greco

Cited by 18 publications

References 0 publications

An Esterel compiler for large control-dominated systems

An Esterel compiler for large control-dominated systems

Parameterized Dataflow Scenarios

Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs

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