Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs

Abstract

Abstract-When designing DSP applications for implementation on field programmable gate arrays (FPGAs), it is often important to minimize consumption of limited FPGA resources while satisfying real-time performance constraints. In this paper, we develop efficient techniques to determine dataflow graph buffer sizes that guarantee throughput-optimal execution when mapping synchronous dataflow (SDF) representations of DSP applications onto FPGAs. Our techniques are based on a novel two-actor SDF graph Model (TASM), which efficiently captures the behavior and costs associated with SDF graph edges (flowgraph connections). With our proposed techniques, designers can automatically generate upper bounds on SDF graph buffer distributions that realize maximum achievable throughput performance for the corresponding applications. Furthermore, our proposed techinque is characterized by low polynomial time complexity, which is useful for rapid prototyping in DSP system design.

Actors with stretchable access patterns

“…Synthesis and comparisons between these different approaches can be found in Refs. [18][19][20][21]b u tt h el a t e s t one, SDF-AP, is taken as a reference in this article because it models the actor's behavior in a fashion close to that of real cores on FPGAs. Indeed, access patterns represent the pace of consumption and production of an actor.…”

Design and implementation of real-time signal processing applications on heterogeneous multiprocessor arrays

“…Each wire bundle has an associated set of handshaking signals to indicate data availability and optionally, to provide backpressure for explicit buffer overflow prevention. For subsystems in which dataflow behavior is predictable, we will apply techniques for compile-time buffer analysis and self-timed, synchronization optimization to minimize the use of point-to-point backpressure synchronization [5,10].…”