Communication storage optimization for static dataflow with access patterns under periodic scheduling and throughput constraint

Wang, G.Q.; Allen, River; Andrade, Hugo A.; Sangiovanni-Vincentelli, A.

doi:10.1016/j.compeleceng.2014.05.002

Cited by 9 publications

(10 citation statements)

References 20 publications

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“…The initiation interval of the model execution is 12 cycles (i.e., T = 12), and the iteration latency is 13 cycles (i.e., IL = 13). Given a throughput constraint, a valid buffer-size for each model channel can be computed from the 1-periodic schedule [11] model provided that the system is bounded and deadlock-free. The throughput τ(a) of an actor a is defined as the average number of firings per unit time and is determined using τ(a) = (RV(a) • PR(c) or CR(c))/T.…”

Section: Buffer Size Computationmentioning

confidence: 99%

“…The correct functional operation of the implemented hardware design in accordance with First, the input registers of the source block X are connected to top-level entity ports and then followed by the instantiation of the HW blocks and FIFO channel. The interfacing of the HW blocks with the FIFO is a combinational assignment of output signals (lines [11][12][13][14]. The process implements the FSM that controls the flow of data to or from the FIFO and the details of how it is built are presented in Section 6.…”

Section: Hardware Designmentioning

confidence: 99%

“…Define the computation methods for buffer size allocation and the latency under 1-periodic scheduling [11] and throughput constraints.…”

mentioning

confidence: 99%

“…The PASS schedule is followed by another schedule of a bounded SDF-AP model execution which is referred to as a 1-periodic schedule [11]. The 1-periodic schedule is defined as σ…”

mentioning

confidence: 99%

“…The buffer computation for SDF-AP is briefly explained in [13,14] whereby the constraint formulation is used to iteratively explore the buffer sizes for FIFO channels to the specified throughput. Wang et al [11] generalize this approach and introduce an optimization technique that is based on Integer Linear Programming (ILP) to minimize communication buffers. In this work, we present in Section 3.2, a method to formally compute a buffer size using a 1-periodic schedule which can easily be automated in high-level synthesis tool.…”

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confidence: 99%

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Automatic Configurable Hardware Code Generation for Software-Defined Radios

2018

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The development of software-defined radio (SDR) systems using field-programmable gate arrays (FPGAs) compels designers to reuse pre-existing Intellectual Property (IP) cores in order to meet time-to-market and design efficiency requirements. However, the low-level development difficulties associated with FPGAs hinder productivity, even when the designer is experienced with hardware design. These low-level difficulties include non-standard interfacing methods, component communication and synchronization challenges, complicated timing constraints and processing blocks that need to be customized through time-consuming design tweaks. In this paper, we present a methodology for automated and behavioral integration of dedicated IP cores for rapid prototyping of SDR applications. To maintain high performance of the SDR designs, our methodology integrates IP cores using characteristics of the dataflow model of computation (MoC), namely the static dataflow with access patterns (SDF-AP). We show how the dataflow is mapped onto the low-level model of hardware by efficiently applying low-level based optimizations and using a formal analysis technique that guarantees the correctness of the generated solutions. Furthermore, we demonstrate the capability of our automated hardware design approach by developing eight SDR applications in VHDL. The results show that well-optimized designs are generated and that this can improve productivity while also conserving the hardware resources used.

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Section: Buffer Size Computationmentioning

confidence: 99%

Section: Hardware Designmentioning

confidence: 99%

“…Define the computation methods for buffer size allocation and the latency under 1-periodic scheduling [11] and throughput constraints.…”

mentioning

confidence: 99%

“…The PASS schedule is followed by another schedule of a bounded SDF-AP model execution which is referred to as a 1-periodic schedule [11]. The 1-periodic schedule is defined as σ…”

mentioning

confidence: 99%

mentioning

confidence: 99%

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