Heterogeneous integration of ReRAM crossbars in 180nm CMOS BEoL process

Sandrini, Jury; Thammasack, Maxime; Demirci, Tuğba; Gaillardon, Pierre-Emmanuel; Sacchetto, Davide; Micheli, Giovanni De; Leblebici, Yusuf

doi:10.1016/j.mee.2015.03.011

Cited by 11 publications

(6 citation statements)

References 7 publications

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“…The measured working voltages are compatible with the selected CMOS technology and suitable for low-voltage applications. This study extends our previous work [15] and [16] by considering a novel electrical characterization methodology enabling to overcome the forming current peaks (Section II-D). This procedure improves the electrical characteristics of the memory, even for 1R configurations.…”

Section: Introductionsupporting

confidence: 54%

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology

Sandrini

Barlas

Thammasack

et al. 2016

IEEE J. Emerg. Sel. Topics Circuits Syst.

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This work presents the co-integration of resistive random access memory crossbars within a 180 nm Read-Write CMOS chip.-based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of-the-Line. Two different strategies, consisting in insertion of an tunnel barrier layer and the design of a dedicated CMOS read circuit, have been developed in order to increase the cell high-to-low resistance ratio of a factor of 1000 and to reduce the sneak-path current effects by one order of magnitude. The ReRAM cells have been integrated directly on a standard CMOS foundry chip, enabling low cost ReRAM-CMOS integration. The integrated memories show a set and reset voltages of and 1.3 V, respectively. The measured operating voltages are compatible for low-voltage applications.Index Terms-Heterogeneous integration, passive crossbar array, post-processing, read-write circuit, resistive ramdom access memories (ReRAMs).

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Section: Introductionsupporting

confidence: 54%

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology

Sandrini

Barlas

Thammasack

et al. 2016

IEEE J. Emerg. Sel. Topics Circuits Syst.

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“…This work is motivated by the greatest advantage of OxRAMs to be fabricated with low thermal budget, allowing their implementation into the Back-End-Of-the-Line (i.e. on top of CMOS transistors) with high integration density [15]. Moreover, as OxRAMs resistance can be programmed, closed-loop OpAmp parameters can be set dynamically.…”

Section: Introductionmentioning

confidence: 99%

Configurable Operational Amplifier Architectures Based on Oxide Resistive RAMs

Aziza

Dufaza

Perez

et al. 2019

J CIRCUIT SYST COMP

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This paper introduces memristor-based operational amplifiers (OpAmps) in which semiconductor resistors are suppressed and replaced by memristors. The ability of the memristive elements to hold several resistance states is exploited to design programmable closed-loop OpAmps. An inverting OpAmp, an integrator and a differentiator are studied. Such designs are developed based on a calibrated memristor model, and offer dynamic configurability to realize different gains and corner frequencies at reduced chip area.

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“…Currently, the interconnect RC scaling methods have reached their limits and there is an urgent need for alternative ways to reduce or remove the latency constraints in CMOS low-k/Cu interconnect. One method is building CBRAM directly into a low-k/Cu interconnects to reduce the latency in connectivity constrained computational devices and the chip's footprint by stacking memory on top of logic circuits [14][15][16]. This is possible since the Cu metal lines and low-k/Cu interconnect already prefigure a potential RS device, and the cross-bar architecture of a typical two-terminal RS device array is essentially the same as a CMOS metal interconnect system.…”

Section: Introductionmentioning

confidence: 99%

Resistive Switching Comparison between Cu/TaO_x/Ru and Cu/TaO_x/Pt Memory Cells

Al‐Mamun

Conlon

et al. 2017

ECS Trans.

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Building nonvolatile memory (NVM) directly into a CMOS lowk/Cu interconnect module would reduce latency in connectivity constrained devices and reduce chip's footprint by stacking memory on top of the logic circuits. One good candidate for NVM is the wellbehaved Cu/TaO x /Pt resistive switching device. However, since platinum (Pt) is not an economic choice for industrial production, a BEOL-compatible replacement of Pt is highly desirable. A good candidate to replace Pt is ruthenium (Ru) which has been already deployed in the CMOS BEOL. Cu/TaO x /Ru and Cu/TaO x /Pt devices were manufactured with the latter device used as a benchmark for the Ru device performance assessment. The electric characterization of both devices has shown many similarities and some notable differences. Compared with Cu/TaO x /Pt, Cu/TaO x /Ru device shows less reliable set and reset switching characteristics due to the different formation, shape and rupture of the conductive filament.

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Heterogeneous integration of ReRAM crossbars in 180nm CMOS BEoL process

Cited by 11 publications

References 7 publications

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology

Configurable Operational Amplifier Architectures Based on Oxide Resistive RAMs

Resistive Switching Comparison between Cu/TaO_x/Ru and Cu/TaO_x/Pt Memory Cells

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Heterogeneous integration of ReRAM crossbars in 180nm CMOS BEoL process

Cited by 11 publications

References 7 publications

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology

Configurable Operational Amplifier Architectures Based on Oxide Resistive RAMs

Resistive Switching Comparison between Cu/TaOx/Ru and Cu/TaOx/Pt Memory Cells

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Resistive Switching Comparison between Cu/TaO_x/Ru and Cu/TaO_x/Pt Memory Cells