Heterogeneous Integration of PoP

Lau, John H.

doi:10.1007/978-981-13-7224-7_7

Cited by 5 publications

(2 citation statements)

References 21 publications

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“…Moreover, a single packaging body can realize multiple functions. Figure 13 shows a typical application of a logic device and a memory device combination in a PoP package used in the Apple iPhone 5s [44]. The top package is a 1 GB LPDD3 RAM chip (11 mm × 7.8 mm) developed by Elpida (now Micron), which is internally interconnected using wire bonding via three rows of 456 solder balls in the FBGA (fine-pitch ball grid array) package substrate.…”

Section: Pop Structurementioning

confidence: 99%

“…The development of advanced, next-generation FOWLP (Fan-Out Wafer-Level Package) technology [51] has fully addressed the shortcomings of the above technologies and been gradually applied in PoP packaging [44] (as shown in Figure 15). This technology often uses a rewiring layer on both sides of the package and a through-hole via to penetrate the plastic fan-out area at the package edge, reducing the package thickness to approximately 0.25 mm.…”

Section: Pop Structurementioning

confidence: 99%

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Survey of Reliability Research on 3D Packaged Memory

Zhou

et al. 2023

Electronics

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As the core carrier of information storage, a semiconductor memory device is a basic product with a large volume that is widespread in the integrated circuit industry. With the rapid development of semiconductor manufacturing processes and materials, the internal structure of memory has gradually shifted from a 2D planar packaging structure to a 3D packaging structure to meet industry demands for high-frequency, high-speed, and large-capacity devices with low power consumption. However, advanced 3D packaging technology can pose some reliability risks, making devices prone to failure, especially when used in harsh environmental conditions, including temperature changes, high temperature and humidity levels, and mechanical stress. In this paper, the authors introduce the typical structure characteristics of 3D packaged memory; analyze the reasons for device failure caused by stress; summarize current research methods that utilize temperature, mechanical and hygrothermal theories, and failure models; and present future challenges and directions regarding the reliability research of 3D packaged memory.

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Section: Pop Structurementioning

confidence: 99%

Section: Pop Structurementioning

confidence: 99%