Heterogeneous high performance computing modules for next generation onboard processing

Marshall, Joseph R.; Rickard, Dale; Sova, Danielle; Miller, Heinz; Lapihuska, Robert; Dennis, A N Gookyi; Graziano, Michael

doi:10.1109/aero.2017.7943645

Cited by 3 publications

(2 citation statements)

References 8 publications

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“…Nowadays state-of-the-art reliable designs in aerospace applications either employ special-purpose radiation-hardened chips [4], [5], which are much slower than commercial ones, or rely on traditional duplication/triplication of the system and on a bit-wise comparison of the produced results [6], [7]. In all cases, the incurred performance degradation is significant.…”

Section: Introductionmentioning

confidence: 99%

A Smart Fault Detection Scheme for Reliable Image Processing Applications

Biasielli

Bolchini

Cassano

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Traditional fault detection/tolerance techniques exploit multiple instances of the nominal processing and then perform a bit-wise comparison of the outputs to detect the occurrence of faults. In specific application scenarios, e.g., image/signal processing, the elaboration has an inherent degree of fault tolerance because it is possible to use the output even in the presence of slight alterations. In these contexts, the classical bit-wise comparison may be inefficient. Indeed, it may lead to conservatively discard outputs that have been only slightly altered by the fault and that could still be usefully exploited. In this paper, we propose a smart checking scheme based on Convolutional Neural Networks that rather than distinguishing between faulty and not faulty images, discriminates between usable and not usable images according to the ability of the end user to correctly process the output. The experimental evaluation shows that this solution enables an execution time saving of about 6.35% with a 99.42% accuracy, on average.

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Section: Introductionmentioning

confidence: 99%

A Smart Fault Detection Scheme for Reliable Image Processing Applications

Biasielli

Bolchini

Cassano

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

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“…Over the past few years, there has been a significant increase in number of satellites launched into space. To enhance the success rate for satellites to complete their critical mission, one of the key considerations is the onboard data processing capabilities [1]- [2]. This has led to using high performance digital signal processors (DSPs) which are unfortunately highly sensitive to radiation-induced soft errors [3].…”

Section: Introductionmentioning

confidence: 99%

Single-Event-Transient Resilient Memory for DSP in Space Applications

Lwin

Sivaramakrishnan

Chong

et al. 2018

2018 IEEE 23rd International Conference on Digital Signal Processing (DSP)

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We present a radiation-hardened-by-design (RHBD) memory design that mitigates Single-Event-Transients (SETs), Single-Event-Upsets (SEUs) and Dual-Event-Upsets (DEUs), hence significantly enhancing the reliability of digital signal processors (DSPs) for space applications. We achieve these attributes by combining a Triple-Interlocked Cell (TICE) SRAM cell array and a Triple Modular Redundancy (TMR) voter. The TICE SRAM cells therein self-correct SEUs and DEUs. The TMR voter eliminates SETs. Our proposed RHBD TICE SRAM cells integrated with the TMR voter are also hardened by the layout/sizing RHBD practices. By means of the 128×9-bit memory implementation @ 65nm CMOS, we show that our memory design is inherent SEU-and DEU-tolerant, and has 94.83% SET reduction and 92.05% Triple-Event-Upset (TEU) reduction when compared to the memory design embodying the 8-transistor (8-T) SRAM cells.

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