Single-Event-Transient Resilient Memory for DSP in Space Applications

Abstract

We present a radiation-hardened-by-design (RHBD) memory design that mitigates Single-Event-Transients (SETs), Single-Event-Upsets (SEUs) and Dual-Event-Upsets (DEUs), hence significantly enhancing the reliability of digital signal processors (DSPs) for space applications. We achieve these attributes by combining a Triple-Interlocked Cell (TICE) SRAM cell array and a Triple Modular Redundancy (TMR) voter. The TICE SRAM cells therein self-correct SEUs and DEUs. The TMR voter eliminates SETs. Our proposed RHBD TICE SRAM cells integrated with the TMR voter are also hardened by the layout/sizing RHBD practices. By means of the 128×9-bit memory implementation @ 65nm CMOS, we show that our memory design is inherent SEU-and DEU-tolerant, and has 94.83% SET reduction and 92.05% Triple-Event-Upset (TEU) reduction when compared to the memory design embodying the 8-transistor (8-T) SRAM cells.

Probability Formulation of Soft Error in Memory Circuit

“…In the case of memory circuits, however, parity bit and checking are employed. This hardening technique involves the generation of a parity value which is then attached to the data (Lwin et al, 2019). When the data is retrieved, a checker will compare the stored parity bit to the one attached to the retrieved data and indicate whether an error has occurred.…”