Heterogeneous computer architectures: An image processing pipeline for optical metrology

Reichenbach, Marc; Seidler, Ralf; Fey, Dietmar

doi:10.1109/reconfig.2012.6416755

Cited by 3 publications

(1 citation statement)

References 12 publications

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“…Previous research has found that a heterogeneous computing system [1], [2] can reduce computation time by partitioning algorithms to processing units (CPU, GPU, or FPGA) best suited for the particular workload. System-on-Chips from Xilinx and Altera with both FPGA fabric and ARM processors on a single die show promise in accelerating applications like cognitive radio that utilize both parallel and sequential processing but have tight timing requirements.…”

Section: Introductionmentioning

confidence: 99%

Reducing Processing Latency with a Heterogeneous FPGA-Processor Framework

Pendlum¹,

Leeser²,

Chowdhury³

2014

2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-Both Xilinx and Altera have released SoCs that tightly couple programmable logic with a dual core Cortex A9 ARM processor. These SoCs show promise in accelerating applications that exploit both the FPGA's parallel processing architecture and the CPU's sequential processing. For example, before accessing a wireless channel, a cognitive radio does spectrum sensing to detect channel occupancy and then makes a decision based on spectrum policies. Spectrum sensing maps well to FPGA fabric, while spectrum decision can be implemented with a CPU. Both algorithms are highly sensitive to latency as a faster decision improves spectrum utilization. This paper introduces CRASH: Cognitive Radio Accelerated with Software and Hardware -a new software and programmable logic framework for Xilinx's Zynq SoC targeting cognitive radio. We implement spectrum sensing and the spectrum decision in three configurations: both algorithms in the FPGA, both in software only, and spectrum sensing on the FPGA and spectrum decision on the CPU. We measure the end-to-end latency to detect and acquire unoccupied spectrum for these configurations. Results show that CRASH can successfully partition algorithms between FPGA and CPU and reduce processing latency.

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Section: Introductionmentioning

confidence: 99%