Fast image processing for optical metrology utilizing heterogeneous computer architectures

Reichenbach, Marc; Seidler, Ralf; Pfundt, Benjamin; Fey, Dietmar

doi:10.1016/j.compeleceng.2013.09.008

Cited by 7 publications

(1 citation statement)

References 10 publications

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“…For the pipelined design method, the article [13] proposed an extremely pipelined FPGA implementation of a lossy hyperspectral image compression algorithm by using very-high-speed integrated circuit hardware description language (VHDL). In article [14], the authors combined the advantages of multicore CPUs, GPUs, and FPGAs to build a heterogeneous image processing pipelined architecture for the Hartman-Shack adaptive optical system. The pipelined design method can increase the data throughput and reduce the latency of the whole system.…”

Section: Background a Related Workmentioning

confidence: 99%

FPGA-Based Implementation of Ship Detection for Satellite On-Board Processing

Chen

Shi

et al. 2022

IEEE J. Sel. Top. Appl. Earth Observations Remote Sensing

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At present, the raw echo data captured by spaceborne SAR is usually downlinked to the ground stations for imaging and analysis. If the SAR data can be processed on-board, the processing results could be transmitted to users directly through broadcast distribution, which can greatly reduce the delay time for emergency applications. However, on-board processing implementation faces many challenges due to the space radiation environment and limited resources of the satellite. In this paper, an FPGA-based implementation of ship detection for on-board processing is proposed, which has high efficiency in logic and memory resources. First, the hardware-oriented clustering approach is proposed. Image processing operations with similar regularity of data access can be mapped in one processing engine, which can reduce the employment of logic resources. Second, the concept of the data-buffering cycle (DBC) is proposed. The DBC provides a method to analyze the intermediate data and optimize the memory reuse. Finally, based on the above optimization methods, the FPGA-based implementation for a ship detection algorithm is presented. Compared with the traditional methods, the experimental results show the efficacy of our proposed method with lower consumption in logic and memory resources.

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Section: Background a Related Workmentioning

confidence: 99%