Hetero-epitaxial growth of InP on Si substrates by LP-MOVPE

Horikawa, H.; Kawai, Yoshio; Akiyama, Masahiro; Sakuta, Masaaki

doi:10.1016/0022-0248(88)90577-5

Cited by 20 publications

(6 citation statements)

References 4 publications

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“…Unlike the GaAs/Si, the InP/Si heteroepitaxy normally adopts the intermediate (graded) buffer layers because of the large lattice mismatch between InP and Si (~8%). The prevailing material commonly used for the intermediate buffer is GaAs [166][167][168][169]. The most typical approach for growing InP on Si is employing the mature multi-step growth of GaAs on Si with strained-layer superlattices filtering the TDs [149,170,171].…”

Section: Intermediate Buffer Layermentioning

confidence: 99%

“…Crystals 2020, 10, x FOR PEER REVIEW 16 of 40 commonly used for the intermediate buffer is GaAs [166][167][168][169]. The most typical approach for growing InP on Si is employing the mature multi-step growth of GaAs on Si with strained-layer superlattices filtering the TDs [149,170,171].…”

Section: Epitaxial Lateral Overgrowthmentioning

confidence: 99%

“…In a similar mechanism of TCA, post-growth annealing (PGA), carried out after completing the growth, has also been widely employed to reduce the TDD of GaAs [207][208][209]. For the InP/Si, TCA or PGA has also been applied to improve the crystal quality [168,169,210,211]. However, the effect of thermal annealing on the defect reduction is not as dramatic as in GaAs/Si because the difference of CTE between InP and Si is relatively small; thus, the dislocation motion by thermally-driven stress is limited.…”

Section: Thermal Annealingmentioning

confidence: 99%

“…It is also revealed that the optimized indium composition and GaAs thickness in SLSs were 0.18 and 10 nm, respectively. In Figure 15d, it was For the InP/Si, TCA or PGA has also been applied to improve the crystal quality [168,169,210,211]. However, the effect of thermal annealing on the defect reduction is not as dramatic as in GaAs/Si because the difference of CTE between InP and Si is relatively small; thus, the dislocation motion by thermally-driven stress is limited.…”

Section: Strained-layer Superlattices Defect Filter Layermentioning

confidence: 99%

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Heteroepitaxial Growth of III-V Semiconductors on Silicon

et al. 2020

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Monolithic integration of III-V semiconductor devices on Silicon (Si) has long been of great interest in photonic integrated circuits (PICs), as well as traditional integrated circuits (ICs), since it provides enormous potential benefits, including versatile functionality, low-cost, large-area production, and dense integration. However, the material dissimilarity between III-V and Si, such as lattice constant, coefficient of thermal expansion, and polarity, introduces a high density of various defects during the growth of III-V on Si. In order to tackle these issues, a variety of growth techniques have been developed so far, leading to the demonstration of high-quality III-V materials and optoelectronic devices monolithically grown on various Si-based platform. In this paper, the recent advances in the heteroepitaxial growth of III-V on Si substrates, particularly GaAs and InP, are discussed. After introducing the fundamental and technical challenges for III-V-on-Si heteroepitaxy, we discuss recent approaches for resolving growth issues and future direction towards monolithic integration of III-V on Si platform.

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Section: Intermediate Buffer Layermentioning

confidence: 99%

Section: Epitaxial Lateral Overgrowthmentioning

confidence: 99%

Section: Thermal Annealingmentioning

confidence: 99%

Section: Strained-layer Superlattices Defect Filter Layermentioning

confidence: 99%

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Heteroepitaxial Growth of III-V Semiconductors on Silicon

et al. 2020

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“…III-V layer growth on Si is complicated by lattice mismatch, thermal expansion coefficient mismatch and polarity related issues [11][12][13]. In the case of nanowires, the lattice mismatch and thermal expansion coefficient mismatch problems are partially eliminated for smaller particle sizes due to the possibility of strain relaxation at the bottom of the nanowires [14,15].…”

Section: Introductionmentioning

confidence: 99%

High vertical yield InP nanowire growth on Si(111) using a thin buffer layer

et al. 2013

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We demonstrate the growth of InP nanowires on Si(111) using a thin InP buffer layer. The buffer layer is grown using a two-step procedure. The initial layer formation is ensured by using a very low growth temperature. An extremely high V/III ratio is necessary to prevent In droplet formation at this low temperature. The second layer is grown on the initial layer at a higher temperature and we find that post-growth annealing of the buffer layer does not improve its crystal quality significantly. It is found that the layers inherently have the (111)B polarity. Nanowires grown on this buffer layer have the same morphology and optical properties as nanowires grown on InP (111)B substrates. The vertical yield of the nanowires grown on the buffer layer is over 97% and we also find that crystal defects in the buffer layer do not affect the morphology, vertical yield or optical properties of the nanowires significantly.

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Indium Triorganyls

Weidlein¹

1991

In Organoindium Compounds

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Hetero-epitaxial growth of InP on Si substrates by LP-MOVPE

Cited by 20 publications

References 4 publications

Heteroepitaxial Growth of III-V Semiconductors on Silicon

Heteroepitaxial Growth of III-V Semiconductors on Silicon

High vertical yield InP nanowire growth on Si(111) using a thin buffer layer

Indium Triorganyls

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