Heavy ions test result on a 65nm Sparc-V8 radiation-hard microprocessor

Bottoni, Cyril; Glorieux, Maximilien; Daveau, Jean-Marc; Gasiot, Gilles; Abouzeid, Fady; Clerc, Sylvain; Naviner, Lírida Alves de Barros; Roché, Philippe

doi:10.1109/irps.2014.6861096

Cited by 16 publications

(9 citation statements)

References 14 publications

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“…The fault tree is divided into 7 levels, each representing a stage of the pipeline. For this experiment, the probabilities used for the failure rates in the model are derived from the cross-section values reported in [15].…”

Section: Failure Estimation Of the Sparc V8 Architecture With Tdftsmentioning

confidence: 99%

“…Secondly, to determine the probability of each type of trap error generated over a period of time. To this end, the probabilities of soft-error events utilized in our model are derived from the cross-section values obtained through the radiation bombardment of a LEON3 design conducted and published in [15]. Furthermore, the work in [15] also contains a fault-injection simulation experiment.…”

Section: Failure Estimation Of the Sparc V8 Architecture With Tdftsmentioning

confidence: 99%

“…Finally, the proposed methodology is used to analyze the 7-stage integer pipeline of a Leon-3 microprocessor. The obtained results are compared with radiation and simulation tests from the literature [15]. Our results demonstrate that regular FTA methods are inadequate for the analysis of systems that are exposed to temporal faults.…”

Section: Introductionmentioning

confidence: 99%

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Towards an Accurate Probabilistic Modeling and Statistical Analysis of Temporal Faults via Temporal Dynamic Fault-Trees (TDFTs)

et al. 2019

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Fault tree (FT) is a standardized notation for representing relationships between a system's reliability and the faults and/or the events associated with it. However, the existing FT fault models are only capable of portraying permanent events in the system. This is a major hindrance since these models fail to reflect accurately the other classes of faults, such as soft-faults, which are often temporary events that usually disappear after the source of the interference is no longer present. This paper proposes a new fault tree modeling paradigm, to capture the impact of temporal events in systems, called temporal dynamic fault trees (TDFTs). TDFTs are utilized to model the characteristics and dependencies between different temporal events, soft-faults, and permanent faults. These features are integrated into the proposed probabilistic models of the temporal gates, which are modeled as priced-timed automata. This paper also proposes a new FT analysis methodology, based on statistical model checking, designed to circumvent the state-explosion problem that is inherent to other model-checking approaches. The proposed analysis is able to evaluate the impact of temporal faults in systems, as well as to estimate the reliability and availability of the system over extended periods of time. The experiments reported in this paper demonstrate the versatility and scalability of the proposed approach. For instance, the results display the impact that temporal events may have in a digital system. Our observations indicate that while regular soft-fault analyses tend to underestimate metrics such as system reliability, TDFT analysis shows remarkable consistency with radiation testing, with differences of under 2%, in the conducted analysis.

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Section: Failure Estimation Of the Sparc V8 Architecture With Tdftsmentioning

confidence: 99%

Section: Failure Estimation Of the Sparc V8 Architecture With Tdftsmentioning

confidence: 99%

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Towards an Accurate Probabilistic Modeling and Statistical Analysis of Temporal Faults via Temporal Dynamic Fault-Trees (TDFTs)

et al. 2019

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“…The SER estimation methods can be analytical, as in [2][3][4], simulated fault-injection, as in [5][6][7][8], emulated fault-injection, as in [9][10][11], or radiation tests, as in [12][13][14]. However, except for the radiation tests, they do not deal directly with the SER, as it requires the ionising particle flux.…”

Section: Introductionmentioning

confidence: 99%

Soft-Error Vulnerability Estimation Approach Based on the SET Susceptibility of Each Gate

2019

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Soft-Error Vulnerability (SEV) is a parameter used to evaluate the robustness of a circuit to the induced Soft Errors (SEs). There are many techniques for SEV estimation, including analytical, electrical and logic simulations, and emulation-based approaches. Each of them has advantages and disadvantages regarding estimation time, resources consumption, accuracy, and restrictions over the analysed circuit. Concerning the ionising radiation effects, some analytical and electrical simulation approaches take into account how the circuit topology and the applied input patterns affect their susceptibilities to Single Event Transient (SET) at the gate level. On the other hand, logic simulation and emulation techniques usually ignore these SET susceptibilities. In this context, we propose a logic simulation-based probability-aware approach for SEV estimation that takes into account the specific SET susceptibility of each circuit gate. For a given operational scenario, we extract the input patterns applied to each gate and calculate its specific SET susceptibility. For the 38 analysed benchmark circuits, we obtained a reduction from 15.27% to 0.68% in the average SEV estimation error, when comparing the estimated value to a reference obtained at the transistor level. The results point out an improvement of the SEV estimation process by considering the specific SET susceptibilities.

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“…The SER estimation methods can be analytical, as in [1], simulated fault-injection, as in [2], emulated fault-injection, as in [3], or radiation tests, as in [4]. The radiation tests, in which the real device is irradiated with neutron beams, is considered the most accurate SER estimation method.…”

Section: Introductionmentioning

confidence: 99%

Probability aware fault-injection approach for SER estimation

Armelin

Naviner

d’Amore

2018

2018 IEEE 19th Latin-American Test Symposium (LATS)

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The Soft-Error Rate (SER) estimation is used to predict how electronic systems will respond to the transient electrical pulses induced by the ionizing radiation. SER estimation by radiation test is an accurate method, but it is expensive and requires the real device. Traditional simulation methods incorporate logical, temporal and electrical masking effects while injecting faults at the output of the device's functional elements. Nevertheless, they do not consider the probability of the ionizing radiation to produce a transient fault at the output of each class of functional element. On the other hand, studies in the stochastic computing domain deal with a probabilistic faultinjection approach. Since many concomitant faults among the elements may occur, the fault probability of each element is treated independently. This leads to the use of one Pseudo-Random Number Generator (PRNG) and a probability comparator for each functional element. However, the analysis of a single fault is usually enough for SER estimation. In this context, this work presents a different approach for probability-aware faultinjection, in which a weighted distribution of faults is defined considering the relative fault probability of each functional element. This approach enables the use of just one PRNG and a decoder for the entire device, instead of a pair 'PRNGcomparator' per element, leading to a significant reduction in logic blocks consumption. For the example analyzed in this study, the use of relative fault probability decreases the number of logic blocks from 875 (adopting independent fault probability) to 495.

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Heavy ions test result on a 65nm Sparc-V8 radiation-hard microprocessor

Cited by 16 publications

References 14 publications

Towards an Accurate Probabilistic Modeling and Statistical Analysis of Temporal Faults via Temporal Dynamic Fault-Trees (TDFTs)

Towards an Accurate Probabilistic Modeling and Statistical Analysis of Temporal Faults via Temporal Dynamic Fault-Trees (TDFTs)

Soft-Error Vulnerability Estimation Approach Based on the SET Susceptibility of Each Gate

Probability aware fault-injection approach for SER estimation

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