Heavy Ion SEU Test Data for 32nm SOI Flip-Flops

Quinn, R. C.; Kauppila, J. S.; Loveless, T. D.; Maharrey, J. A.; Rowe, J. D.; McCurdy, Michael W.; Zhang, E. X.; Alles, Michael L.; Bhuva, B. L.; Reed, Robert A.; Holman, W.T.; Bounasser, M.; Lilja, K.; Massengill, L.W.

doi:10.1109/redw.2015.7336712

Cited by 14 publications

(8 citation statements)

References 6 publications

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“…Thus, these specially designed hardened flip-flops, which tolerate SEMUs through charge cancellation, are required. Hardened flip-flops have been experimentally validated using radiation experiments on test chips fabricated in 90nm, 45nm, 40nm, 32nm, 28nm, 20nm, and 14nm nodes in both bulk and SOI technologies and can be incorporated into standard cell libraries (i.e., standard cell design guidelines are satisfied) [19], [37], [38], [39], [40], [41]. The LEAP-ctrl flip-flop is a special design, which can operate in resilient (high resilience, high power) and economy (low resilience, low power) modes.…”

Section: Resilience Librarymentioning

confidence: 99%

Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)

Cheng

Mirkhani

Szafaryn

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We present CLEAR (Cross-Layer Exploration for Architecting Resilience), a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to reliability failures: achieve desired resilience targets at minimal costs (energy, power, execution time, area) by combining resilience techniques across various layers of the system stack (circuit, logic, architecture, software, algorithm). This is also referred to as cross-layer resilience. In this paper, we focus on radiation-induced soft errors in processor cores. We address both single-event upsets (SEUs) and single-event multiple upsets (SEMUs) in terrestrial environments. Our framework automatically and systematically explores the large space of comprehensive resilience techniques and their combinations across various layers of the system stack (586 cross-layer combinations in this paper), derives cost-effective solutions that achieve resilience targets at minimal costs, and provides guidelines for the design of new resilience techniques. We demonstrate the practicality and effectiveness of our framework using two diverse designs: a simple, in-order processor core and a complex, out-of-order processor core. Our results demonstrate that a carefully optimized combination of circuit-level hardening, logic-level parity checking, and micro-architectural recovery provides a highly cost-effective soft error resilience solution for general-purpose processor cores. For example, a 50× improvement in silent data corruption rate is achieved at only 2.1% energy cost for an out-of-order core (6.1% for an in-order core) with no speed impact. However, (application-aware) selective circuit-level hardening alone, guided by a thorough analysis of the effects of soft errors on application benchmarks, provides a cost-effective soft error resilience solution as well (with ~1% additional energy cost for a 50× improvement in silent data corruption rate).Index Terms-Cross-layer resilience; soft errors I. INTRODUCTION HIS paper addresses the cross-layer resilience challenge for designing robust digital systems: given a set of resilience techniques at various abstraction layers (circuit, logic, architecture, software, algorithm), how does one protect a given design from radiation-induced soft errors using (perhaps) a combination of these techniques, across multiple abstraction layers, such that overall soft error resilience targets are met at minimal costs (energy, power, execution time, area)? Specific soft error resilience targets addressed in this paper are: Silent Data Corruption (SDC), where an error causes the system to output an incorrect result without error indication; and, Detected but Uncorrected Error (DUE), This research is supported in part by DARPA, DTRA, NSF, and SRC. The views expressed are those of the authors and do not reflect the official policy or position of the Department of Defense or the U.S. Government.E. Cheng, S. Mirkhani, and S. Mitra are with Stanford University (e-mail: eccheng@ stanford.edu).H. Cho is w...

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Section: Resilience Librarymentioning

confidence: 99%

Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)

Cheng

Mirkhani

Szafaryn

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The standard Dual Interlocked Storage Cell (DICE) has been applied to DFFs in deep-submicron planar Complementary Metal Oxide Semiconductor (CMOS) technologies to achieve low Single Event Upset (SEU) rates [3,4]. However, the critical charges of SEU for DFF cells are not high, especially for the advanced nanoscale technologies [3][4][5][6]. Moreover, the heavy ion-induced charge sharing phenomenon among adjacent sensitive nodes increases the probability of upsets, making the basic hardening techniques ineffective [5,6].…”

Section: Introductionmentioning

confidence: 99%

“…However, the critical charges of SEU for DFF cells are not high, especially for the advanced nanoscale technologies [3][4][5][6]. Moreover, the heavy ion-induced charge sharing phenomenon among adjacent sensitive nodes increases the probability of upsets, making the basic hardening techniques ineffective [5,6]. Thus, it is essential to characterize the radiation tolerance and evaluate the effectiveness of hardening strategies of nanoscale circuits.…”

Section: Introductionmentioning

confidence: 99%

“…In recent years, some heavy ion irradiation results for the standard and hardened DFFs of different process nodes have been characterized, and the main SEU cross sections in the published literature are shown in Table 1 [3][4][5][6]. The heavy ion irradiation results for the 65 nm standard DFF, basic DICE DFF, and a temporal-DICE DFF are presented in Ref.…”

Section: Introductionmentioning

confidence: 99%

“…At the LET value of 60 MeV•cm 2 •mg −1 , the upset cross sections for the 28 nm designs are statistically identical, whereas there is still a noticeable improvement for the 40 nm capacitive hardened DFF, indicating that for the advanced technologies, using capacitance to reduce SEU cross-sections for high LET particles is unattractive [4]. The SEU cross-sections for a broad scope of parameters including the clock frequency and angle of incidence are characterized for the hardened and unhardened DFFs in 32 nm Silicon on Isolator (SOI) technology [5]. The 32 nm DICE DFF is improved in SEU tolerance, while the influence of LET values and frequency is significant.…”

Section: Introductionmentioning

confidence: 99%

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SEU Tolerance Efficiency of Multiple Layout-Hardened 28 nm DICE D Flip-Flops

Chi

Cai

et al. 2022

Electronics

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Three layout-hardened Dual Interlocked Storage Cell (DICE) D Flip-Flops (DFFs) were designed and manufactured based on an advanced 28 nm planar technology. The systematic vertical and tilt heavy ion irradiations demonstrated that the DICE structure contributes to radiation tolerance. However, it is hard to achieve immunity from a Single Event Upset (SEU), even when a ~3-µm well isolation is utilized. The SEU mitigation of the hardened DFFs was affected by the data patterns and clock signals due to the imbalance in the number of upset nodes. When the clock signal equalled 0, no error was observed in 181Ta irradiation, indicating that the DICE DFFs are SEU tolerant in vertical irradiation owing to their reasonable isolation of sensitive volumes. The divergences of SEU cross-sections were enlarged by our specially designed joint change of tilt incidences for both the along-cell and cross-cell irradiation of heavy ions. The evaluations of SEU for both the vertical and tilt irradiations assist with eliminating the overestimation of SEU tolerance and guarantee the in-orbit safety of spacecraft in harsh radiation environments.

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