Heavy-Ion Induced Single Event Transients in Sub-7nm Bulk and SOI NSFETs

Jha, Chandan Kumar; Rathi, Aarti; Yogi, Pritam; Aditya, Kritika; Dixit, Abhisek

doi:10.1109/icee50728.2020.9776740

Cited by 1 publication

(1 citation statement)

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“…[1][2][3] The SET induced by the highenergy particles can result in a voltage level upset or a transient current latching of combinational logic, further dominating the soft error responses in CMOS integrated circuits design. [4][5][6] This transient will become more obvious with the decreasing transistor sizes and the reducing nodal capacitances. 7,8) Layout-based radiation hardening techniques can alleviate the single-event effect to some extent for both N-type metal-oxide-semiconductor (NMOS) and P-type metal-oxide-semiconductor (PMOS).…”

Section: Introductionmentioning

confidence: 99%

Investigation of PVT variation on single-event transient effect assisted with hardened layout techniques

Liang¹,

Luo²,

Sun³

et al. 2022

Jpn. J. Appl. Phys.

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With the aggressively scaled technology, the single-event transient (SET) in the integrated circuits is regarded as one of the critical threats to the system reliability, where the hardening efficiency strongly depends on the randomness of striking positions and process-voltage-temperature (PVT) variations. To enhance the SET robustness and improve the immunity to PVT variations, different layout-based hardening techniques are proposed and compared. Moreover, the tolerance of PVT for hardened layouts and the underlying physics reasons are investigated by technology-computer-aided-design (TCAD) simulations. The simulation reveals that the techniques combining the split active area (SAA), gapless well and source (GWS), and the selectively implanted deep N-well (SIDNW) enable to reduce the transient pulse width as well as mitigate the variations from PVT and hit position.

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