Heavy-Ion Induced SETs in 32nm SOI Inverter Chains

Maharrey, J. A.; Kauppila, J. S.; Quinn, R. C.; Loveless, T. D.; Zhang, En Xia; Holman, W.T.; Bhuva, B. L.; Massengill, L.W.

doi:10.1109/redw.2015.7336717

Cited by 4 publications

(2 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The bottle neck of this method is that, to quantify the pulse width, multiple identical hits are needed. Another technique uses a chain of identical cells, which forms a signal delay chain, to quantify the transient pulse width by counting the number of flipped cells [13]- [16]. In 65 nm technology, several papers characterized the SET pulse duration based on this method.…”

Section: Introductionmentioning

confidence: 99%

Characterization of the Total Charge and Time Duration for Single-Event Transient Voltage Pulses in a 65-nm CMOS Technology

Berti

Wouters

et al. 2022

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

This paper presents the circuits and heavy-ion irradiation test results of a Single-Event Transient (SET) measurement chip in a 65 nm CMOS technology. The measurements contain two parts: total SET ionization charge and SET pulse duration. Transistors with different types and dimensions were implemented as victim devices to evaluate how transistor parameters impact the SET effects. Additionally, SET variation from different supply voltages was also investigated. The test chip has been tested under a heavy-ion beam with an effective LET (Linear Energy Transfer) from 20.4 to 88.35 MeV•cm 2 /mg using a 0 o to 45 o incidence angle.

show abstract

Section: Introductionmentioning

confidence: 99%

Characterization of the Total Charge and Time Duration for Single-Event Transient Voltage Pulses in a 65-nm CMOS Technology

Berti

Wouters

et al. 2022

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

show abstract

“…For SEE mitigation in highly-scaled bulk CMOS, several soft error mitigation techniques, including a proper utilization of redundant storage nodes and stacked transistors to isolate sensitive nodes, have been proposed [4]- [15], but limited benefits are obtained [1]- [3]. Though silicon-on-insulator (SOI) technology is often considered to be more robust to soft errors than bulk CMOS technologies, highly-scaled SOI circuits are still not soft errors immune, especially in the case of low linear energy transfer (LET) heavy-ion irradiation [4], [5]. The soft error rate in hardened SOI cells are found to be orders of The associate editor coordinating the review of this manuscript and approving it for publication was Woorham Bae .…”

Section: Introductionmentioning

confidence: 99%

Characterization of Heavy Ion Induced SET Features in 22-nm FD-SOI Testing Circuits

Cai

Liu

et al. 2020

IEEE Access

View full text Add to dashboard Cite

With device scaling-down, circuits appear more susceptible to transient faults especially for the bulk silicon process. Thus, FD-SOI technology has been widely popular in serious radiation environment due to its high radiation-tolerance inherence created by an additional BOX layer. In this work, seven different inverter chains with two kinds of core voltages, four kinds of channel areas and a stack inverter chain are designed to investigate the SET in advanced 22 nm FD-SOI CMOS technology. A NAND chain is also designed and used for comparison with inverter chains. The sensitivities of diverse SET targets are characterized with different core voltages and heavy-ion tilts. Results showed that the inverter size and the driving current can dominate the occurrence and width distribution of transient pulses. Besides, heavy-ion strike angle, LET, and charge sharing can also affect the pulse width. Though a high LET can deposit adequate energy, the widest pulses are measured in low-LET 84 Kr ion irradiation, rather than in high-LET ions' irradiation, which are attributed to the pulse quenching effect and being investigated by Hspice simulation. The LET dependency and low voltage induced SET widening are all observed in irradiation tests and verified by circuit-level pulse injection. All of the SET sensitive targets are distinguished. The results are highly effective for the designers to suppress and correct the SET-oriented errors to achieve a radiation robust system. INDEX TERMS Fully-depleted silicon-on-insulator (FD-SOI), heavy ions, inverter, single event transient.

show abstract

Effect of Transistor Variants on Single-Event Transients at the 14-/16-nm Bulk FinFET Technology Generation

Harrington

Maharrey

Kauppila

et al. 2018

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

Heavy-Ion Induced SETs in 32nm SOI Inverter Chains

Cited by 4 publications

References 4 publications

Characterization of the Total Charge and Time Duration for Single-Event Transient Voltage Pulses in a 65-nm CMOS Technology

Characterization of the Total Charge and Time Duration for Single-Event Transient Voltage Pulses in a 65-nm CMOS Technology

Characterization of Heavy Ion Induced SET Features in 22-nm FD-SOI Testing Circuits

Effect of Transistor Variants on Single-Event Transients at the 14-/16-nm Bulk FinFET Technology Generation

Contact Info

Product

Resources

About