Effect of Transistor Variants on Single-Event Transients at the 14-/16-nm Bulk FinFET Technology Generation

Harrington, R. C.; Maharrey, J. A.; Kauppila, J. S.; Nsengiyumva, Patrick; Ball, D. R.; Haeffner, T. D.; Zhang, E. X.; Bhuva, B. L.; Massengill, L.W.

doi:10.1109/tns.2018.2843260

Cited by 19 publications

(5 citation statements)

References 19 publications

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“…Overall, an increased cross-section for the circuits based on the LP technology is noticed. This behavior is in agreement with the literature, in which it was shown that the increase on the threshold voltage leads to degradation of driving strength capability [40][41][42]. The NAND gates are the most sensitive to this V TH variation with a cross-section increase of 95% and 85% for the NAND_X1 and NAND_X2, respectively.…”

Section: Set Immunity Of Standard-cell Logic Gatessupporting

confidence: 92%

Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

et al. 2020

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Due to the intrinsic masking effects of combinational circuits in digital designs, Single-Event Transient (SET) effects were considered irrelevant compared to the data rupture caused by Single-Event Upset (SEU) effects. However, the importance of considering SET in Very-Large-System-Integration (VLSI) circuits increases given the reduction of the transistor dimensions and the logic data path depth in advanced technology nodes. Accordingly, the threat of SET in electronics systems for space applications must be carefully addressed along with the SEU characterization. In this work, a systematic prediction methodology to assess and improve the SET immunity of digital circuits is presented. Further, the applicability to full-custom and cell-based design methodologies are discussed, and an analysis based on signal probability and pin assignment is proposed to achieve a more application-efficient SET-aware optimization of synthesized circuits. For instance, a SET-aware pin assignment can provide a reduction of 37% and 16% on the SET rate of a NOR gate for a Geostationary Orbit (GEO) and the International Space Station (ISS) orbit, respectively.

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Section: Set Immunity Of Standard-cell Logic Gatessupporting

confidence: 92%

Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

et al. 2020

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“…However, the fringing electric field is enhanced due to the ferroelectric material polarization, which increases the current driven capability 13 . It has been indicated that the device with a larger driven current was better immunity to SET 3 , 6 . This means that the increase of the driven current leads to the decrease of the collected charge by the drain.…”

Section: Impact Of Spacer On Setmentioning

confidence: 99%

Single event response of ferroelectric spacer engineered SOI FinFET at 14 nm technology node

Liu

Zhu

2023

Sci Rep

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The impact of spacer on the single event response of SOI FinFET at 14 nm technology node is investigated. Based on the device TCAD model, well-calibrated by the experimental data, it is found that the spacer presents the enhancement on single event transient (SET) compared with no spacer configuration. For single spacer configuration, due to enhanced gate control capability and fringing field, the increments in SET current peak and collected charge for HfO2 are the least with 2.21%, 0.97%, respectively. Four possible dual ferroelectric spacer configurations are proposed. The placement of ferroelectric spacer at S side and HfO2 spacer at D side brings to weaken SET with the variation in current peak and collected charge by 6.93%, 1.86%, respectively. The reason may be its enhanced gate controllability over the S/D extension region, which improves the driven current. With linear energy transfer increasing, SET current peak and collected charge present the trend of increase while the bipolar amplification coefficient reduces.

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“…The reason may be that due to TID irradiation, the threshold voltage of the device reduces, which leads to the driven current of the device increase. A larger driven current gets a good immunity to SET [16,20], resulting in the collected charge decrease. Simultaneously, after TID irradiation, large numbers of the positive hole trap charges are captured by the gate oxide [16].…”

Section: Set Response Of Finfet After Tidmentioning

confidence: 99%

Single event transient of SOI FinFET with total ionizing dose irradiation

Liu,

Zhou,

Qian

2023

Vib. proced.

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Total ionizing dose (TID) irradiation impacts the device leakage currents or threshold voltage, which affects the single event transient (SET) vulnerability of electronics under radiation environment. SET response of SOI FinFET at 14 nm technology node after TID exposure is carried out at different dose level. Results show that the drain current peak presents a slight fluctuant with total dose, while the collected charge and the bipolar amplification coefficient first decrease with total dose and then increase. The potential reason is also discussed from competing mechanisms associated with decreasing threshold voltage from TID irradiation and increasing the drain diffuse current from the potential of the channel.

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Effect of Transistor Variants on Single-Event Transients at the 14-/16-nm Bulk FinFET Technology Generation

Cited by 19 publications

References 19 publications

Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

Single event response of ferroelectric spacer engineered SOI FinFET at 14 nm technology node

Single event transient of SOI FinFET with total ionizing dose irradiation

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