HARPE: A Harvard-based processing element tailored for partial dynamic reconfigurable architectures

Montone, A.; Rana, Vincenzo; Santambrogio, Marco D.; Sciuto, D.

doi:10.1109/ipdps.2008.4536507

Cited by 3 publications

(1 citation statement)

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“…A second solution consists of performing a partial dynamic reconfiguration of BRAM blocks, as described in [12]. This reconfiguration has to be performed by the reconfiguration controller, but in this case there is no need to directly connect it to each BRAM block, since these elements are updated by the controller using the configuration memory; thus, no area overhead is introduced.…”

Section: Path Reconfigurationmentioning

confidence: 99%

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

Rana

Atienza

Santambrogio

et al. 2010

IFIP Advances in Information and Communication Technology

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Summary. Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systems-on-Chips (SoCs). However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of running applications may be highly sub-optimal for another set of applications. In this context, methods that can lead to versatility enhancements of initial NoC designs to changing working conditions, imposed by variable sets of executed real-life applications at each moment in time, are very important for designing competitive NoCs in industrial SoCs.In this work, we present a run-time reconfigurable NoC framework based on the partial dynamic reconfiguration capabilities of Field-Programmable Gate Arrays (FPGAs). This new NoC framework can dynamically create/delete express lines between SoC components (implementing dynamically circuit-switching channels) and perform run-time NoC topology and routing-table reconfigurations to handle interconnection congestion, with a very limited performance overhead. Moreover, we show in our experimental results that the addition of these dynamic reconfiguration capabilities into basic NoCs using our framework only implies a very limited area overhead (around 10% on average) with respect to the initial NoC designs; thus, it can bring great benefits when compared to traditional non-reconfigurable NoC design approaches for worst-case bandwidth requirements in SoCs with many possible sets of running applications.

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Section: Path Reconfigurationmentioning

confidence: 99%