Hardware support for real-time operating systems

Kohout, Paul; Ganesh, Brinda; Jacob, Bruce

doi:10.1145/944645.944656

Cited by 54 publications

(13 citation statements)

References 8 publications

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“…from Rate Monotonic Algorithm-RMA to Earliest Deadline First-EDF depending on application requirements) with a time penalty imposed by the reconfigurable logic of the FPGA used for the scheduler implementation. The same idea of having an external hardware scheduler separated from the processor is widely used [2], [5], [6], [8]. Bloom, Parmer, Narahari and Simha [3] also leave the priority queues to be managed by the hardware layer whereas the software layer deals with the scheduling policy.…”

Section: Related Workmentioning

confidence: 99%

Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers — Concept and theory of operation

Dodiu

Găitan

2012

2012 IEEE International Conference on Electro/Information Technology

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System response time is a key element in hard real time systems. In classical Real Time Operating Systems (RTOS) based on software schedulers, overhead and jitter are a major problem when the number of tasks and the rate of context switches are high. Increased values for those parameters over admissible values can lead to performance degradation, increased power consumption or even deadline misses. If a part of the scheduling components or the entire functionality is moved from software to hardware, a significant improvement in task switching times can be achieved. This paper presents a custom designed multi pipeline register architecture (MPRA) that has a dedicated hardware scheduler unit integrated into the CPU.

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Section: Related Workmentioning

confidence: 99%

Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers — Concept and theory of operation

Dodiu

Găitan

2012

2012 IEEE International Conference on Electro/Information Technology

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“…Other approaches try to find a good balance between flexibility of software and performance of pure hardware-based design. For this purpose they implement only a sub-part of the scheduler such as task priorities management with dedicated hardware queues [14]. • Time management: notion of time is given by the periodic activation of the system clock tick interrupt.…”

Section: ) Timing Observation Servicementioning

confidence: 99%

“…This operation increases the overhead according to the number of tasks and tick resolution. A traditional way to minimize this overhead is to use hardware delay counters associated to each task [14], [15], but still this approach lacks some flexibility. [16] proposed a timer service migration of the Xenomai hard real time kernel on FPGA on embedded Linux, but this approach does not provide any component based reconfiguration capabilities.…”

Section: ) Timing Observation Servicementioning

confidence: 99%

A Hardware/Software CBSE Framework for RTOS Services: The Timing Service Case Study

Rubini

Babau

Boukhobza

2012

2012 IEEE 15th International Conference on Computational Science and Engineering

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The ever-growing complexity of today's embedded system, and the extra functional requirements like temporal or energy consumption constraints are one of the more exciting challenges for today's embedded system designers. Keeping the design space as open as possible, especially with regards to the hardware (HW) or software (SW) assignments of the system functions, are key points to minimize the project risk.In this paper, we propose a HW/SW Component-Based System Engineering framework for Real-Time Operating Systems (RTOS) services. The proposed approach combines the flexibility and power of software component based approach with the adaptability and performance of reconfigurable hardware architectures. This study focuses on the RTOS timing services case study. We show in this paper the value of such an approach especially in a context of precise time-driven requirements.

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“…A significant amount of work deals with the implementation of operating system services in hardware, particularly task management services [3] [4] [5] [6]. Regarding communication services, we highlight the work carried out by Yau [7], where an ORB (Object Request Broker) is implemented in hardware.…”

Section: Related Workmentioning

confidence: 99%

An Infrastructure for Hardware-Software Co-Design of Embedded Real-Time Java Applications

Silva

Andrews

Pereira

et al. 2008

2008 11th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC)

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The partitioning of applications into hardware and software is an important issue in embedded systems, opening room for high level specifications as well as the exploration of different implementation strategies. This paper presents a software architecture to specify threads in hardware in the context of the Real Time Specification for Java (RTSJ) standard. There is a Java class that encapsulates hardware components, providing an abstraction layer to the application developer. Below this Java class, a wrapper hardware component provides a standard interface between RTSJ-based software components and the hardware that implements the thread behavior. This approach provides a high flexibility in choosing either a hardware or software implementation, allowing to postpone hardware/software partitioning to the very end of system development. The paper includes some quantitative data from an example containing hardware and software threads. While both implementations are compatible with the rest of the application from an interface pointof-view, they lead to very different timing and area results.

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Hardware support for real-time operating systems

Cited by 54 publications

References 8 publications

Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers — Concept and theory of operation

Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers — Concept and theory of operation

A Hardware/Software CBSE Framework for RTOS Services: The Timing Service Case Study

An Infrastructure for Hardware-Software Co-Design of Embedded Real-Time Java Applications

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Hardware support for real-time operating systems

Cited by 54 publications

References 8 publications

Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers &#x2014; Concept and theory of operation

Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers &#x2014; Concept and theory of operation

A Hardware/Software CBSE Framework for RTOS Services: The Timing Service Case Study

An Infrastructure for Hardware-Software Co-Design of Embedded Real-Time Java Applications

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Product

Resources

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Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers — Concept and theory of operation

Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers — Concept and theory of operation