Hardware Support for Broadcast and Reduce in MPSoC

Peng, Yuanxi; Saldaña, Manuel; Chow, Paul

doi:10.1109/fpl.2011.34

Cited by 14 publications

(10 citation statements)

References 9 publications

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“…Peng et al [10] describe extra control circuitry added to a NoC which allows for broadcasts using crossbars. Moadeli and Vanderbauwhede [11] describe a NoC protocol which allows for high-level wormhole multicast for data destined for multiple applications.…”

Section: A Previous Multi-core Sensing Systemsmentioning

confidence: 99%

A Broadcast-Enabled Sensing System for Embedded Multi-core Processors

Zhao

Burleson

et al. 2014

2014 IEEE Computer Society Annual Symposium on VLSI

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Contemporary multi-core architectures deployed in embedded systems are expected to function near the operational limits of temperature, voltage, and device wear-out. To date, most on-chip sensing systems have been designed to collect and use sensor information for these parameters locally. In this paper, a new sensing system to enhance multi-core dependability which supports both the local and global distribution of sensing data in embedded processors is considered. The benefit of the new sensing architecture is verified using the broadcast of microarchitectural parameter signatures which can be used to identify impending voltage droops. Low-latency broadcasts are supported for a range of sensor data transfer rates. Up to a 9% performance improvement for a 16-core system is determined via the use of the distributed voltage droop sensor information (5.4% on average). The entire sensing system, including broadcasting resources, requires about 2.6% of multi-core area.

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Section: A Previous Multi-core Sensing Systemsmentioning

confidence: 99%

A Broadcast-Enabled Sensing System for Embedded Multi-core Processors

Zhao

Burleson

et al. 2014

2014 IEEE Computer Society Annual Symposium on VLSI

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“…However, these approaches cannot be directly used in NoC infrastructure under different constraints. For on-chip multicore systems, Peng et al [2011] considered the NoC designs for lowoverhead broadcast and reduced transmission but did not consider the communication protocol.…”

Section: Related Workmentioning

confidence: 99%

Adaptive communication mechanism for accelerating MPI functions in NoC-based multicore processors

Huang

Wang

Xiao

et al. 2013

ACM Trans. Archit. Code Optim.

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Multicore designs have emerged as the dominant organization for future high-performance microprocessors. Communication in such designs is often enabled by Networks-on-Chip (NoCs). A new trend in such architectures is to fit a Message Passing Interface (MPI) programming model on NoCs to achieve optimal parallel application performance. A key issue in designing MPI over NoCs is communication protocol, which has not been explored in previous research.This article advocates a hardware-supported communication mechanism using a protocol-adaptive approach to adjust to varying NoC configurations (e.g., number of buffers) and workload behavior (e.g., number of messages). We propose the ADaptive Communication Mechanism (ADCM), a hybrid protocol that involves behavior similar to buffered communication when sufficient buffer is available in the receiver to that similar to a synchronous protocol when buffers in the receiver are limited. ADCM adapts dynamically by deciding communication protocol on a per-request basis using a local estimate of recent buffer utilization. ADCM attempts to combine both the advantages of buffered and synchronous communication modes to achieve enhanced throughput and performance. Simulations of various workloads show that the proposed communication mechanism can be effectively used in future NoC designs.

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“…The subsequent work on the TMD-MPI approach has considered the NoC designs (TMD-MPE, message passing engine) for low-overhead transmission [38,44]. The software overhead problem will worsen when high-speed parallel communication channels are used to transmit messages.…”

Section: Background 287mentioning

confidence: 99%

“…This work presents TMD-MPI as a subset of MPI, the definition and extension of the packet format to communication systems in different FPGAs, as well as the intra-FPGA using a simple NoC architecture. Peng [38] considered the NoC designs for low overhead broadcast and reduced transmission but did not consider the communication protocol. In Ref.…”

Section: Introductionmentioning

confidence: 99%

Network-on-chip customizations for message passing interface primitives††Part of this research was first presented at the IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors (ASAP-2012) [23].

2015

Networks-on-Chip

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285286 CHAPTER 9 NoC customizations for message passing interface primitives INTRODUCTIONTo enable continuous exponential performance scaling for parallel applications, multicore designs have become the dominant organization forms for future highperformance microprocessors. The availability of massive on-chip transistors to hardware architects gives rise to the expectation that the exponential growth in the number of cores on a single processor will soon facilitate the integration of hundreds of cores into mainstream computers [3].Traditional shared bus interconnects are incapable of sustaining the multicore architecture with the appropriate degree of scalability and required bandwidth to facilitate communication among a large number of cores. Moreover, full crossbars become impractical with the growing number of cores. Networks-on-chip (NoCs) are becoming the most viable solution to mitigate this problem. The NoCs are conceived to be more cost-effective than the bus in terms of traffic scalability, area, and power in large-scale systems. Such networks are ideal for component reuse, design modularity, plug-and-play, and scalability while avoiding issues with global wire delays. Recent proposals, such as the 64-core TILE64 processor from Tilera [51], Intel's 80-core Teraflops chip [22], Arteris's NoC interconnect IPs [2], and NXP-Philips' AEtheral NoC [18], have successfully demonstrated the potential effectiveness of NoC designs.However, most existing general-purpose NoC designs do not support the highlevel programming model well. This condition compromises performance and efficiency when programs are mapped onto NoC-based hardware architectures. That is, most current programming model optimizations aiming to address these problems maintain a firm abstraction of the interconnection network fabric as a communication medium: protocol optimizations comprise end-to-end messages between requestor and answer nodes, whereas network optimizations separately aim at reducing the communication latency and improving the throughput for data messages. Reducing or even eliminating the gap between the multicore programming models with the underlying NoC-based hardware is a demanding task. Thus, a key challenge in multicore research is the provision of efficient support for parallel programming models to boost applications by exploiting all hardware features available in NoCbased multicore architectures.A large body of research has recently focused on integrating the message passing interface (MPI) standard into multicore architectures. The MPI is a standard, public-domain, platform-independent communications library for message-passing programming. Numerous applications have now been ported to or developed for the MPI model. The performance optimization of such models is a necessity for multicore architectures. These research efforts include the systems-on chip (SoC) MPI library implemented on a Xilinx Virtex field-programmable gate array (FPGA) [30], the rMPI targeting embedded systems using MIT's Raw processor [39], the TMD-MP...

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Hardware Support for Broadcast and Reduce in MPSoC

Cited by 14 publications

References 9 publications

A Broadcast-Enabled Sensing System for Embedded Multi-core Processors

A Broadcast-Enabled Sensing System for Embedded Multi-core Processors

Adaptive communication mechanism for accelerating MPI functions in NoC-based multicore processors

Network-on-chip customizations for message passing interface primitives††Part of this research was first presented at the IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors (ASAP-2012) [23].

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