Hardware/software partitioning with iterative improvement heuristics

Eles, P.; Peng, Zebo; Kuchcinski, K.; Doboli, A.

doi:10.1109/isss.1996.565881

Cited by 14 publications

(6 citation statements)

References 15 publications

(13 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…2 Architecture for an ID token be done. Most of the cost functions proposed is focused on decreasing time and area [12,13]. However, considering biometric system necessities, a new cost function is proposed:…”

Section: Hw/sw Co-design For Id Tokensmentioning

confidence: 99%

Optimisation of biometric ID tokens by using hardware/software co-design

et al. 2012

View full text Add to dashboard Cite

In current society, the necessity of recognising people is increasing every day. Logical or physical access is restricted to authorised users, which in many cases have to provide tokens where their personal information is stored. At the same time, biometrics proposes a feasible solution for the recognition problem. The combination of both solutions is coming up front. However, up till now, owing to processing restrictions, these tokens are just able to store data and perform the last steps of the biometric recognition process. In this study, the authors propose a new system where tokens are based on hardware/ software (HW/SW) co-design, which allows computing most of the biometric process in them. This proposal covers several aspects which these systems are subject to, taking advantages of the two platforms they use for reducing computational time or HW area, and also to increase security or minimise misidentification errors. For testing this proposal, an Iris ID token has been implemented, showing different design alternatives adapted to different work scenarios.

show abstract

Section: Hw/sw Co-design For Id Tokensmentioning

confidence: 99%

Optimisation of biometric ID tokens by using hardware/software co-design

et al. 2012

View full text Add to dashboard Cite

show abstract

“…Most such techniques partition at the granularity of arithmetic operations, differing in the partitioning heuristics employed. Clustering heuristics are used in [14] and [15], integer-linear programming in [16] and [17], manual partitioning in [18], and iterative-improvement heuristics in [19] and [20]. Other techniques for hardware partitioning operate at a higher level of granularity, such as in [21] where processes and subroutines are partitioned among ASIC's using clustering, iterative-improvement, and manual techniques.…”

Section: B Partitioningmentioning

confidence: 99%

SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design

Gajski¹,

Vahid

Narayan³

et al. 1998

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-System-level design issues are gaining increasing attention, as behavioral synthesis tools and methodologies mature. We present the SpecSyn system-level design environment, which supports the new specify-explore-refine (SER) design paradigm. This three-step approach to design includes precise specification of system functionality, rapid exploration of numerous systemlevel design options, and refinement of the specification into one reflecting the chosen option. A system-level design option consists of an allocation of system components, such as standard and custom processors, memories, and buses, and a partitioning of functionality among those components. After refinement, the functionality assigned to each component can then be synthesized to hardware or compiled to software. We describe the issues and approaches for each part of the SpecSyn environment. The new paradigm and environment are expected to lead to a more than ten times reduction in design time, and our experiments support this expectation.

show abstract

“…Tosca [Antoniazzi 1994] uses clustering to partition a hierarchical-concurrent finite-state machine. Tabu-search is used to partition procedures in Eles et al [1996].…”

Section: Hardware/software Functional Partitioningmentioning

confidence: 99%

Functional partitioning improvements over structural partitioning for packaging constraints and synthesis

Vahid

Le²,

Hsu

1998

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

Incorporating functional partitioning into a synthesis methodology leads to several important advantages. In functional partitioning, we first partition a functional specification into smaller subspecifications and then synthesize structure for each, in contrast to the current approach of first synthesizing structure for the entire specification and then partitioning that structure. One advantage is the improvement in I/O performance and package count, when partitioning among hardware blocks with size and I/O constraints, such as FPGAs or blocks within an ASIC. A second advantage is reduction in synthesis runtimes. We describe these important advantages, concluding that further research on functional partitioning can lead to improved results from synthesis environments.

show abstract

Hardware/software partitioning with iterative improvement heuristics

Abstract: Abstract

Cited by 14 publications

References 15 publications

Optimisation of biometric ID tokens by using hardware/software co-design

Optimisation of biometric ID tokens by using hardware/software co-design

SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design

Functional partitioning improvements over structural partitioning for packaging constraints and synthesis

Contact Info

Product

Resources

About