Functional partitioning improvements over structural partitioning for packaging constraints and synthesis

Vahid, Frank; Le, Thuyen; Hsu, Yu-Chin

doi:10.1145/290833.290841

Cited by 15 publications

(10 citation statements)

References 33 publications

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“…Traditional approaches [83,19,48] to integrate HLS and spatial partitioning perform exploration and estimation along with partitioning. In the traditional heterogeneous model of HLS and spatial partitioning, the partitioner invokes a HLS estimator to obtain the area/latency of each spatial partition.…”

Section: Figure 51: Sparcs Design Automation System For Rcsmentioning

confidence: 99%

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Computer Aided Engineering for Reconfigurable Computing (CAERC)

Vemuri¹

2001

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The public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Department of Defense, Washington Headquarters Services, Directorate for Information Operations and Reports (0704-0188), 1215 Jefferson Davis Highway, Suite 1204, Arlington, VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to any penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number. PLEASE DO NOT RETURN YOUR FORM TO THE ABOVE ADDRESS. REPORT DATE (DD-MM-YY)October 2001 2. REPORT TYPE Approved for public release; distribution unlimited. SUPPLEMENTARY NOTES ABSTRACT (Maximum 200 Words)Synthesis and Partitioning for Adaptive and Reconfigurable Computing Systems (SPARCS) is a computer aided engineering environment for reconfigurable computers. SPARCS contains software implementations of a variety of methods and algorithms for various subproblems for automating the task of producing designs for multi-FPGA (Field Programmable Gate Array) based reconfigurable computers. The SPARCS system includes tools for temporal partitioning, spatial partitioning, high-level synthesis, physical design, and arbiter synthesis. This is a comprehensive report on the SPARCS project, describing various techniques developed for solving these problems. In addition, this report contains some experimental results demonstrating the effectiveness of the SPARCS tools. Reconfigurable processors consisting of a sea of uncommitted FPGAs offer the same performance advantages of custom computing while retaining the flexibility of general purpose instruction architectures. In 1996, at the begining of this project, it was predicted that in near future reconfigurable processors can offer lOOx performance improvement over contemporary microprocessors, and 10-100x reduction in power/gate, 20x progress in density, and l,000,000x reduction in reconfiguration time compared to current reconfigurable devices.Unfortunately, state-of-the-art design synthesis methodologies were able to use perhaps 50-75% of the available gates at 30-50% of the maximum clocking rate of single reprogrammable device and were woefully inadequate in synthesizing multi-device systems. In order to deliver the performance expectations of reconfigurable architectures, dramatic improvements in the synthesis tools were necessary in both directions: (1) ability to synthesize to multiple device architectures, and, (2) improvement in utilization and delivered performance of each device. The goal of this project was to develop a coherent design synthesis and partitioning environment for co...

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Section: Figure 51: Sparcs Design Automation System For Rcsmentioning

confidence: 99%

“…Behavioral partitioning is a pre-synthesis partitioning while structural partitioning is done after HLS. Studies [38,48,20,19] comparing Behavioral and RTL partitioning show the superiority of the former for large designs.…”

Section: Introductionmentioning

confidence: 99%

Computer Aided Engineering for Reconfigurable Computing (CAERC)

Vemuri¹

2001

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“…Behavioral partitioning is a presynthesis partitioning while RTL partitioning is done after high-level synthesis. Various studies [1] show the superiority of behavioral over structural partitioning.…”

Section: Introductionmentioning

confidence: 99%

Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints

Lakshmikanthan

Govindarajan

Srinivasan

et al. 2000

Lecture Notes in Computer Science

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“…Tasks dissipate an average energy of 4 nJ per cycle with a variability of 3.5 nJ per cycle. We use an SOC area constraint of 70 mm 2 . The communication link is the same as the one in Section 5.1.…”

Section: Results On Randomized Task Graphsmentioning

confidence: 99%

“…In structural partitioning, synthesis is done first, followed by the partitioning of the resultant structure. A detailed comparison of these approaches, showing advantages of functional partitioning, is given in [2]. Our approach uses functional partitioning.…”

Section: Introductionmentioning

confidence: 99%