Hardware/software managed scratchpad memory for embedded system

Janapsatya, Andhi; Parameswaran, Sri; Ignjatović, Aleksandar

doi:10.1109/iccad.2004.1382603

Cited by 31 publications

(48 citation statements)

References 11 publications

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“…As a result, the contents in the local memory area have higher security than those in cache. The local memory power consumption [6], [7] is also smaller than that of the traditional cache system. Not only can performance and power consumption be improved using local memory, but security and reliability can also be enhanced.…”

Section: Local Memorymentioning

confidence: 84%

Robust Lightweight Embedded Virtualization Layer Design with Simple Hardware Assistance

Lin

Kinebuchi

Nakajima

2012

IEICE Trans. Inf. & Syst.

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SUMMARYIn this paper, we propose a virtualization architecture for a multi-core embedded system to provide more system reliability and security while maintaining performance and without introducing additional special hardware supports or implementing a complex protection mechanism in the virtualization layer. Embedded systems, especially consumer electronics, have often used virtualization. Virtualization is not a new technique, as there are various uses for both GPOS (General Purpose Operating System) and RTOS (Real Time Operating System). The surge of the multicore platforms in embedded systems also helps consolidate the virtualization system for better performance and lower power consumption. Embedded virtualization design usually uses two approaches. The first is to use the traditional VMM, but it is too complicated for use in the embedded environment without additional special hardware support. The other approach uses the microkernel, which imposes a modular design. The guest systems, however, would suffer from considerable modifications in this approach, as the microkernel allows guest systems to run in the user space. For some RTOSes and their applications originally running in the kernel space, this second approach is more difficult to use because those codes use many privileged instructions. To achieve better reliability and keep the virtualization layer design lightweight, this work uses a common hardware component adopted in multi-core embedded processors. In most embedded platforms, vendors provide additional on-chip local memory for each physical core, and these local memory areas are only private to their cores. By taking advantage of this memory architecture, we can mitigate the above-mentioned problems at once. We choose to re-map the virtualization layer's program on the local memory, called SPUMONE, which runs all guest systems in the kernel space. Doing so, it can provide additional reliability and security for the entire system because the SPUMONE design in a multi-core platform has each instance installed on a separate processor core. This design differs from traditional virtualization layer design, and the content of each SPUMONE is inaccessible to the others. We also achieve this goal without adding overhead to the overall performance.

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Section: Local Memorymentioning

confidence: 84%

Robust Lightweight Embedded Virtualization Layer Design with Simple Hardware Assistance

Lin

Kinebuchi

Nakajima

2012

IEICE Trans. Inf. & Syst.

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“…First, those of a static approximation where the contents of the SPM are assigned in advance and remain unchanged during program execution [1], [2], and [4]. Second, the ones that perform a dynamic update of the SPM contents at run time: Egger et al [5] [6] and [7], Hyungmin Cho et al [8], Janapsatyat et al [9], Steinke et al [10], Polleti et al [11] , Lian Li et al [13] and Doosan et al [19]. The latter have the advantage of adapting the contents of the SPM to the program run but at the cost of periodically reloading the SPM contents.…”

Section: Related Workmentioning

confidence: 99%

“…There are some papers that propose hardware extensions to better control the SPM [9], [11], [12], and [13]. In [9] Janapsatyat et al introduce a special set of instructions at compile time in a number of key points using a heuristic algorithm, which trigger a hardware controller that manages the flow of data to the SPM.…”

Section: Related Workmentioning

confidence: 99%

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Architecture Extensions for Efficient Management of Scratch-Pad Memory

Busquets-Mataix

Catalá

Campoy

2011

Lecture Notes in Computer Science

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Abstract. Nowadays, many embedded processors include in their architecture on-chip static memories, so called scratch-pad memories (SPM). Compared to cache, these memories do not require complex control logic, thus resulting in increased efficiency both in silicon area and energy consumption. Last years, many papers have proposed algorithms to allocate memory segments in SPM in order to enhance its usage. However, very few care about the SPM architecture itself, to make it more controllable, more power efficient and faster. This paper proposes architecture extensions to automatically load code into the SPM whilst it is fetched for execution to reduce the SPM updating delays, which motivates a very dynamic use of the SPM. We test our proposal in a derivation of the Simplescalar simulator, with typical embedded benchmarks. The results show improvements, on average, of 30.6% in energy saving and 7.6% in performance compared to a system with cache.

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“…Many SPM management approaches have been proposed. All the existing approaches can be classified into two categories: static allocation [1,6,10,11,22] and dynamic allocation [2, 3, 12-15, 20, 24, 27]. In the case of static allocation approaches, once an SPM resident is loaded into the SPM, its space in the SPM cannot be allocated to other SPM residents during the execution of the program.…”

Section: Introductionmentioning

confidence: 99%

WCET-aware data selection and allocation for scratchpad memory

Wan

Xue

2012

Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Syst

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In embedded systems, SPM (scratchpad memory) is an attractive alternative to cache memory due to its lower energy consumption and higher predictability of program execution. This paper studies the problem of placing variables of a program into an SPM such that its WCET (worst-case execution time) is minimized. We propose an efficient dynamic approach that comprises two novel heuristics. The first heuristic iteratively selects a most beneficial variable as an SPM resident candidate based on its impact on the k longest paths of the program. The second heuristic incrementally allocates each SPM resident candidate to the SPM based on graph coloring and acyclic graph orientation. We have evaluated our approach by comparing with an ILP-based approach and a longestpath-based greedy approach using the eight benchmarks selected from Powerstone and Mälardalen WCET Benchmark suites under three different SPM configurations. Our approach achieves up to 21% and 43% improvements in WCET reduction over the ILPbased approach and the greedy approach, respectively.

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Hardware/software managed scratchpad memory for embedded system

Cited by 31 publications

References 11 publications

Robust Lightweight Embedded Virtualization Layer Design with Simple Hardware Assistance

Robust Lightweight Embedded Virtualization Layer Design with Simple Hardware Assistance

Architecture Extensions for Efficient Management of Scratch-Pad Memory

WCET-aware data selection and allocation for scratchpad memory

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