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Abstract

Cache memories are commonly avoided in real-time systems because of their unpredictable behavior. Recently, some research has been done to obtain tighter bounds on the worst case execution time (WCET) of cached programs. These techniques usually assume a non preemptive underlying system. However, some techniques can be applied to allow the use of caches in preemptive systems. This paper describes how to incorporate the effect of instruction cache to the Response Time schedulability Analysis (RTA). RTA is an efficient analysis for preemptive fixed priority schedulers. We also compare through simulations the results of such an approach to the previously available CRMA (Cached RMA: cache eflect is incorporated in the utilization based Rate Monotonic schedulability analysis). The results show that the cached version of RTA (CRTA) clearly outpelforms CRMA. MotivationNowadays, the applications of the real-time theory are not limited to the life-critical systems (hard-real time systems), where the cost factor is of secondary importance. Emerging areas like car computers, multimedia computing, gesture recognition, voice interaction, CD-I and the like [ 141, demand real-time capabilities but at a relative low cost, as all consumer products impose this requirement. Yet, some of these applications involve intensive computing tasks and, therefore require a cheap, but powerful hardware platform to be competitive in the marketplace.Microprocessor manufacturers are adopting solutions based on statistical assumptions of the workload to improve the cost-performance ratio. This trend, jointly with big market volumes, allows contemporary processors to achieve a very good cost-performance ratio. On the other hand, since these processors are dedicated to a large audience, they are widely tested increasing their reliability. In conclusion, contemporary processors are good candidates to implement cost-effective real-time applications because they are cheap, powerful and reliable. However, some techniques have to be applied to make those processors more predictable.With caches, a good first step to increase processor utilization is to calculate the worst case execution time (WCET) of tasks taking into account the cache speed-up. Some tools can be used to estimate the WCET of cached programs [13][ 1][11]. These tools typically assume continuity for the code execution, thus no preemption is allowed. This limitation restricts the application of such tools to non preemptive scheduling policies like cyclic executives or cooperative scheduling. However, two actions can be undertaken to make caches suitable for preemptive real-time systems. Firstly, making the cache behavior more predictable (for example using partitioning, locking pieces of code, or simply using easy to model cache configurations). Secondly, modelling the cache behavior to incorporate the cache effects on the schedulability analysis. Using these techniques we can take advantage of the huge research effort committed to date in preemptive systems. Without these techniques, the ...

Locking caches, providing full determinism and good performance, are a very interesting solution to replacing conventional caches in real-time systems. In such systems, temporal correctness must be guaranteed. The use of predictable components, like locking caches, helps the system designer to determine if all the tasks will meet its deadlines. However, when locking caches are used in a static manner, the system performance depends on the instructions loaded and locked in cache. The selection of these instructions may be accomplished through a genetic algorithm. This paper shows the impact of the fitness function in the final performance provided by the real-time system. Three fitness functions have been evaluated, showing differences in the utilisation and performance obtained.

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