Hardware–software design and validation framework for wireless LAN modems

Drosos, Christos; Bisdounis, L.; Metafas, D. E.; Blionas, S.; Tatsaki, A.; Papadopoulos, George

doi:10.1049/ip-cdt:20040496

Cited by 8 publications

(2 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In recent years, mature SoC implementations of WLAN 802.11 wireless MAC has been reported [3], [4]. In contrast, a few published works on 802.16 realization can be found.…”

Section: Introductionmentioning

confidence: 90%

Hardware accelerator IP-core for wireless 802.16 MAC

Holisaz

Shamshiri

Baharvand

et al. 2006

2006 IFIP International Conference on Wireless and Optical Communications Networks

View full text Add to dashboard Cite

In IEEE 802.16 standard, the performance of the Subscriber Station (SS) MAC has to meet the timing constraints for the uplink and downlink transmissions. This requirement implies hardware acceleration of some protocol components through a precise hardware-software partitioning. In this paper, we first model the behavior of the system through high level Specification and Description Language (SDL). After automatic translation of the SDL model into a true C model, a SoPC platform is used for prototype implementation. Analysis and HW/SW partitioning of the generated model is performed to meet 75Mbps throughput required for OFDM-PHY. The proposed hardware accelerator in this paper has been implemented using a 0.13um CMOS technology in order to perform more detailed analysis on the performance of design which is targeted for ASIC applications. Analysis results show efficiency of our proposed design in terms of area and timing while achieving the required throughput on a low-cost embedded-processor based platform.

show abstract

“…In recent years, mature SoC implementations of WLAN 802.11 wireless MAC has been reported [3], [4]. In contrast, a few published works on 802.16 realization can be found.…”

Section: Introductionmentioning

confidence: 90%

Hardware accelerator IP-core for wireless 802.16 MAC

Holisaz

Shamshiri

Baharvand

et al. 2006

2006 IFIP International Conference on Wireless and Optical Communications Networks

View full text Add to dashboard Cite

show abstract

“…Drosos et al present an implementation of an embedded baseband modem terminal for a wireless LAN application on a platform with two ARM CPUs and an FPGA circuit [1]. The system is specified with UML and software parts are created separately for both CPUs with UML automatic code generation tool.…”

Section: Related Workmentioning

confidence: 99%

Configurable Multiprocessor Platform with RTOS for Distributed Execution of UML 2.0 Designed Applications

Arpinen

Kukkala

Salminen

et al. 2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

View full text Add to dashboard Cite

This paper presents the design and full prototype implementation of a configurable multiprocessor platform that supports distributed execution of applications described in UML 2.0. The platform is comprised of multiple Altera Nios II softcore processors and custom hardware accelerators connected by the Heterogeneous IP Block Interconnection (HIBI) communication architecture. Each processor has a local copy of eCos real-time operating system for the scheduling of multiple application threads. The mapping of a UML application into the proposed platform is presented by distributing a WLAN medium access control protocol onto multiple CPUs. The experiments performed on FPGA show that our approach raises system design to a new level. To our knowledge, this is the first real implementation combining a high-level design flow with a synthesizable platform.

show abstract