Hardware-software covalidation: fault models and test generation

Harris, Ian G.

doi:10.1109/hldvt.2001.972822

Cited by 7 publications

(4 citation statements)

References 67 publications

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“…Harris gives a comprehensive overview on RTL ATPG in 2001 [1], in particular on the usage of control/datapath flow graphs (CDFG). This section gives an overview of the different RTL fault models for testability analysis on RTL and/or test pattern generation not mentioned in [1]. Solutions which propose additional test insertion logic are not considered.…”

Section: Survey On Rtl Atpgmentioning

confidence: 99%

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

Strauch¹

2016

Preprint

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This paper starts with a comprehensive survey on RTL ATPG. It then proposes a novel RTL ATPG model based on "Gate Inherent Faults" (GIF). These GIF are extracted from each complex gate (adder, case-statement, etc.) of the RTL source code individually. They are related to the internal logic paths of a complex gate. They are not related to any net/signal in the RTL design. It is observed, that when all GIF on RTL are covered (100%) and the same stimulus is applied, then all gate level stuck-at faults of the netlist are covered (100%) as well. The proposed RTL ATPG model is therefore synthesis independent. This is shown on ITC'99 testcases. The applied semi-automatic test pattern generation process is based on functional simulation.

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Section: Survey On Rtl Atpgmentioning

confidence: 99%

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

Strauch¹

2016

Preprint

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“…A measure of test effectiveness is typically referred to as a coverage metric and many coverage metrics have been developed for both hardware and software testing [1][2][3] . Coverage metrics define a set of criteria, which must be satisfied during simulation to ensure detection of design errors.…”

Section: Introductionmentioning

confidence: 99%

Verifying Complex Interaction between Hardware Processes

Ramineni¹

2009

Journal of Computer Science

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Problem statement: Verification of correct functionality of semiconductor devices has been a challenging problem. Given the device fabrication cost, it is critical to verify the expected functionality using simulations of executable device models before a device manufactured. However, typical industrial scale devices today involve large number of interactions between their components. Complexity of verifying all interactions becomes almost intractable even in simulation. The infeasible interactions need to be eliminated from verification consideration in order to reduce the complexity of the problem. Also an empirical metric of completeness of the verification of such interactions is needed. This metric should provide measure of quality of verification as well as that of degree of confidence in future correct behavior of the device. Metric should guide stimulus generation for simulation so that all aspects of the device functionality can be covered in verification. Existing coverage metrics focus almost exclusively on verification of individual components. Approach: In this study, interactions between device components modeled as independent processes, were considered. The interactions considered between control flow paths in different processes. Present algorithm analyzed the dependency between the control flow paths. It was also determined set of feasible interactions between the control flow paths and pruned out the infeasible ones. Remaining set of feasible interactions constituted our interaction coverage metric. Our metric handled device designs with an arbitrary number of processes. Results: Number of interactions to be considered in simulation-based verification was significantly reduced by our coverage metric using our proposed algorithms. This limited the complexity and scope of stimulus generation to coverage of only set of feasible interactions. Conclusion: Proposed coverage metric was able to provide realistic measure of degree of verification of components interactions as well as effectively guide the test generation process for device designs consisting of an arbitrary number of components

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“…A survey of fault models used for validation of behavioral hardware and software descriptions can be found in [3]. A number of fault models are based on the traversal of paths through the control dataflow graph (CDFG) representing the system behavior.…”

Section: Previous Workmentioning

confidence: 99%

“…Automatic test generation tools cannot be reliably used for design validation until the set of fault models used have been evaluated and are known to ensure the detection of nearly all design errors. Many fault models have been identified in previous research [3] hut the ability of these fault models to ensure detection of real design errors has never been evaluated.…”

Section: Introductionmentioning

confidence: 99%

A method for the evaluation of behavioral fault models

Gaudette

Moussa

Harris

Eighth IEEE International High-Level Design Validation and Test Workshop

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Many fault models have been proposed which attempt to capture design errors in behavioral descriptions, hut these fault models have never been quantitatively evduated. The essential question which must be answered about any fault model is, "If all faults in this model are detected, is the design guaranteed to be correct?" In this paper we present a method to examine the degree to which an arbitrary fault model can ensure the detection of all design errors. The method involves comparing fault coverage to error coverage as defined by a practical design error model which we describe. We have employed our method to perform a limited analysis of the statement and branch coverage fault models.

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Hardware-software covalidation: fault models and test generation

Cited by 7 publications

References 67 publications

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

Verifying Complex Interaction between Hardware Processes

A method for the evaluation of behavioral fault models

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