2006 International Conference on Mechatronics and Automation 2006
DOI: 10.1109/icma.2006.257627
|View full text |Cite
|
Sign up to set email alerts
|

Hardware/Software Co-design of Control Algorithms

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
7
0

Year Published

2008
2008
2014
2014

Publication Types

Select...
3
1

Relationship

1
3

Authors

Journals

citations
Cited by 4 publications
(7 citation statements)
references
References 7 publications
0
7
0
Order By: Relevance
“…The robot is attached to a table by a system of holders for easy and quick emergency disconnection of the mechanism from the station. A field programmable gate array-based controller [10,11] controls the operation of the actuators and tools (a mechanism of needle extension, rotation of an endoscope optics) placed on a platform attached to the robot. The platform also houses the endoscope optics head (rotated by an additional actuator) with a camera and elements for urethral pressure profile measurements.…”
Section: The Concept Of the Demonstration Standmentioning
confidence: 99%
“…The robot is attached to a table by a system of holders for easy and quick emergency disconnection of the mechanism from the station. A field programmable gate array-based controller [10,11] controls the operation of the actuators and tools (a mechanism of needle extension, rotation of an endoscope optics) placed on a platform attached to the robot. The platform also houses the endoscope optics head (rotated by an additional actuator) with a camera and elements for urethral pressure profile measurements.…”
Section: The Concept Of the Demonstration Standmentioning
confidence: 99%
“…In the same context, in [10] the case study is a neural controller for 3 D.o.f parallel robot for milling. This controller is based on neural model of the inverse dynamics of the manipulator, trained on data collected with the use of a computed torque stabilizing controller, and the authors propose that good candidates for hardware implementation are those fragments of an algorithm that can be calculated using only fixedpoint operations, due to the fact that they require less FPGA resources and, therefore, are faster whenever are compared with floating-point modules.…”
Section: Related Workmentioning
confidence: 99%
“…compilers (Quartus, ISE), hardware description languages (Verilog, VHDL), and high-level hardware description languages such as Handel-C (named algorithmic HDL or algorithmic languages for clarity in the thesis), [21], [22], [25]. They allow for synthesis and prototyping of processing units in a relatively short time, skipping tedious low-level design techniques (with some additional power and hardware resources overheads, however), [21], [22] [27], [28]. Since standard C lacks notations typical to hardware, such as parallelism or the passage of time, the concepts are introduced, either as extensions to the relevant language (or via 'pragmas') or are built into the tool and annotated by a programmer against the standard C description.…”
Section: D) Mcu Disadvantagesmentioning
confidence: 99%
“…at low-level (often referred to a hardware-level) and at higher levels (e.g. at system-levels), [27], [136], [137], [138], [139], [140], [141], [142], [143], [144]. The low-level design partitioning is often in a form of design decomposition into multiple clock domains, while the latter approach addresses algorithm partitioning.…”
Section: Algorithm Partitioning Of Fpga-based Designsmentioning
confidence: 99%
See 1 more Smart Citation