A Reconfigurable System Approach to the Direct Kinematics of a 5D.o.fRobotic Manipulator

Abstract

Hardware acceleration in high performance computer systems has a particular interest for many engineering and scientific applications in which a large number of arithmetic operations and transcendental functions must be computed. In this paper a hardware architecture for computing direct kinematics of robot manipulators with 5 degrees of freedom (5 D.o.f ) using floatingpoint arithmetic is presented for 32, 43, and 64 bit-width representations and it is implemented in Field Programmable Gate Arrays (FPGAs). The proposed architecture has been developed using several floating-point libraries for arithmetic and transcendental functions operators, allowing the designer to select (pre-synthesis) a suitable bit-width representation according to the accuracy and dynamic range, as well as the area, elapsed time and power consumption requirements of the application. Synthesis results demonstrate the effectiveness and high performance of the implemented cores on commercial FPGAs. Simulation results have been addressed in order to compute the Mean Square Error (MSE), using the Matlab as statistical estimator, validating the correct behavior of the implemented cores. Additionally, the processing time of the hardware architecture was compared with the same formulation implemented in software, using the PowerPC (FPGA embedded processor), demonstrating that the hardware architecture speeds-up by factor of 1298 the software implementation.

Reconfigurable Computing Applied to Latency Reduction for the Tactile Internet

“…The total time to perform the calculations was 1240 ns. Comparing to the forward kinematics (FK) implementation using 32-bit floating-point proposed by this work, the speedup was 26.38 × over the model presented in [24].…”

“…Some studies demonstrate the benefit of using FPGA to accelerate robotic manipulation algorithms related to haptic systems. A hardware architecture implemented in FPGA for performing the forward kinematics of 5-DoF robots using floating point arithmetic was described in [24]. In this hardware implementation all the forward kinematics calculations were performed within 1.24µs which represents 67 clock cycles in a frequency of 54 MHz.…”

“…As described in Table 4, a hardware model for calculating the forward kinematics of a 5-DoF device is presented in [24]. The proposed hardware was implemented using a 32bit floating-point representation.…”

Acceleration of parallel robot kinematic calculations in FPGA

“…In case of implementing equations in the actual controller, the most important is accuracy and speed of calculations. In this regard, an interesting solution is implementation of the kinematics equations in a controller based on FPGA [13,14].…”

FPGA based hardware accelerator for parallel robot kinematic calculations

“…In the case of implementing equations in actual controller the most important factors are related to accuracy and speed of calculations. In this regard an interesting solution is the implementation of the kinematics equations in a controller based on FPGA [6,7].…”