Hardware RTOS: Custom Scheduler Implementation Based on Multiple Pipeline Registers and MIPS32 Architecture

Zagan, Ionel; Găitan, Vasile Gheorghiţă

doi:10.3390/electronics8020211

Cited by 11 publications

(11 citation statements)

References 24 publications

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“…The remarkability of the architecture is reflected in the name itself by specifying that the pipelined registers are multiplied, which allows the hardware context of the thread being executed to be saved, making it easier to stop an instance of the pipeline at any time and to change the context in a single clock cycle. The multiplication of hardware resources is (partly) illustrated in [ 7 ].…”

Section: Related Workmentioning

confidence: 99%

“…Only one nMPRA hardware instance is active at any given time. An instance of nMPRA execution contains logical combinational blocks of the five pipeline stages (IF, ID, EXECUTE (EX), DATA MEMORY (MEM), and WRITE BACK (WB)), which are common resources shared by all nMPRA instances, as well as those from the private hardware resources associated with the software thread that is being instantiated (GPR, pipeline, and PC; status and control register file; flag file; work registers and/or counters [ 7 ]). A more detailed description of the architecture can be found in [ 6 ] with the appropriate terms that represent the architecture at that time.…”

Section: Related Workmentioning

confidence: 99%

“…Coprocessor 2 is available to the user. The degree of novelty and relevance of the proposed architecture is demonstrated by the results published in the prestigious IEEE TVLSI [ 6 ] and Electronics [ 7 ] journals.…”

Section: Introductionmentioning

confidence: 99%

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An Overview of the nMPRA and nHSE Microarchitectures for Real-Time Applications

Găitan

Zagan

2021

Sensors

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In the context of real-time control systems, it has become possible to obtain temporal resolutions of microseconds due to the development of embedded systems and the Internet of Things (IoT), the optimization of the use of processor hardware, and the improvement of architectures and real-time operating systems (RTOSs). All of these factors, together with current technological developments, have led to efficient central processing unit (CPU) time usage, guaranteeing both the predictability of thread execution and the satisfaction of the timing constraints required by real-time systems (RTSs). This is mainly due to time sharing in embedded RTSs and the pseudo-parallel execution of tasks in single-processor and multi-processor systems. The non-deterministic behavior triggered by asynchronous external interrupts and events in general is due to the fact that, for most commercial RTOSs, the execution of the same instruction ends in a variable number of cycles, primarily due to hazards. The software implementation of RTOS-specific mechanisms may lead to significant delays that can affect deadline requirements for some RTSs. The main objective of this paper was the design and deployment of innovative solutions to improve the performance of RTOSs by implementing their functions in hardware. The obtained architectures are intended to provide feasible scheduling, even if the total CPU utilization is close to the maximum limit. The contributions made by the authors will be followed by the validation of a high-performing microarchitecture, which is expected to allow a thread context switching time and event response time of only one clock cycle each. The main purpose of the research presented in this paper is to improve these factors of RTSs, as well as the implementation of the hardware structure used for the static and dynamic scheduling of tasks, for RTOS mechanisms specific to resource sharing and intertask communication.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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An Overview of the nMPRA and nHSE Microarchitectures for Real-Time Applications

Găitan

Zagan

2021

Sensors

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“…Zagan et al [12] presented scheduling of tasks via the use of a hardware architecture as opposed to a software-based RTOS.…”

Section: Introductionmentioning

confidence: 99%

Task Scheduling to Constrain Peak Current Consumption in Wearable Healthcare Sensors

Sherratt

Janko

Hui³

et al. 2019

Electronics

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Small embedded systems, in our case wearable healthcare devices, have significant engineering challenges to reduce their power consumption for longer battery life, while at the same time supporting ever-increasing processing requirements for more intelligent applications. Research has primarily focused on achieving lower power operation through hardware designs and intelligent methods of scheduling software tasks, all with the objective of minimizing the overall consumed electrical power. However, such an approach inevitably creates points in time where software tasks and peripherals coincide to draw large peaks of electrical current, creating short-term electrical stress for the battery and power regulators, and adding to electromagnetic interference emissions. This position paper proposes that the power profile of an embedded device using a real-time operating system (RTOS) will significantly benefit if the task scheduler is modified to be informed of the electrical current profile required for each task. This enables the task scheduler to schedule tasks that require large amounts of current to be spread over time, thus constraining the peak current that the system will draw. We propose a solution to inform the task scheduler of a tasks' power profile, and we discuss our application scenario, which clearly benefited from the proposal.

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“…An alternative solution for this project could be the nMPRA (Multi Pipeline Register Architecture) processor implementation [25]. Using this processor with functions implemented in the hardware would add extra performance to the system, as well as superior energy efficiency.…”

mentioning

confidence: 99%

Design, Fabrication, and Testing of an IoT Healthcare Cardiac Monitoring Device

et al. 2020

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The expansion of the concept of the Internet of Things (IoT), together with wireless sensor networks, has given rise to a wide range of IoT applications. This paper presents and describes the concept, theory of operation, and practical results of a Telecare-ECG (Electrocardiogram) Monitoring device, designed for the remote monitoring of out-of-hospital cardiac patients. ECG monitoring using the Telecare-ECG Monitor system ensures a better quality of life for patients and greater possibilities for the real-time monitoring and signaling of sporadic cardiac events, by recording instantaneous cardiac arrhythmias captured during certain activities or in the daily environment of the patient; furthermore, hospital resources are less impacted by this device than other devices. In accordance with the novelty and contribution of this paper to the field of ECG investigations, the results obtained in the analysis, testing, and validation of the Telecare-ECG Monitor system refer to the optimization of the functionality of the mobile ECG device under conditions that were as similar to reality as possible.

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Hardware RTOS: Custom Scheduler Implementation Based on Multiple Pipeline Registers and MIPS32 Architecture

Cited by 11 publications

References 24 publications

An Overview of the nMPRA and nHSE Microarchitectures for Real-Time Applications

An Overview of the nMPRA and nHSE Microarchitectures for Real-Time Applications

Task Scheduling to Constrain Peak Current Consumption in Wearable Healthcare Sensors

Design, Fabrication, and Testing of an IoT Healthcare Cardiac Monitoring Device

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