An Overview of the nMPRA and nHSE Microarchitectures for Real-Time Applications

Abstract

In the context of real-time control systems, it has become possible to obtain temporal resolutions of microseconds due to the development of embedded systems and the Internet of Things (IoT), the optimization of the use of processor hardware, and the improvement of architectures and real-time operating systems (RTOSs). All of these factors, together with current technological developments, have led to efficient central processing unit (CPU) time usage, guaranteeing both the predictability of thread execution and the satisfaction of the timing constraints required by real-time systems (RTSs). This is mainly due to time sharing in embedded RTSs and the pseudo-parallel execution of tasks in single-processor and multi-processor systems. The non-deterministic behavior triggered by asynchronous external interrupts and events in general is due to the fact that, for most commercial RTOSs, the execution of the same instruction ends in a variable number of cycles, primarily due to hazards. The software implementation of RTOS-specific mechanisms may lead to significant delays that can affect deadline requirements for some RTSs. The main objective of this paper was the design and deployment of innovative solutions to improve the performance of RTOSs by implementing their functions in hardware. The obtained architectures are intended to provide feasible scheduling, even if the total CPU utilization is close to the maximum limit. The contributions made by the authors will be followed by the validation of a high-performing microarchitecture, which is expected to allow a thread context switching time and event response time of only one clock cycle each. The main purpose of the research presented in this paper is to improve these factors of RTSs, as well as the implementation of the hardware structure used for the static and dynamic scheduling of tasks, for RTOS mechanisms specific to resource sharing and intertask communication.

Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation

“…Thus, we are considering in the future to develop an emulator for the HW_nMPRA_RTOS concept supporting RISC-V, MIPS32, and ARM ISA. The papers [7], [26], [27] present these simulations at the concept level and do not explain the algorithms underlying the implementation of the real-time scheduler. In [7] the basic concept of nMPRA is presented for the first time, with a static Round Robin scheduling.…”

“…In [26] only a basic solution for handling mutex type events is presented. In the overview presented in [27] different ISAs for nMPRA processor support, namely MIPS32, RISC-V and ARM, are reviewed. In this paper, the authors describe the dynamic nHSE scheduler with a prioritybased preemptive execution for each instPi.…”

Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation

“…Finally, the clock signal is generated by the Xilinx ® LogiCORE™ IP Clocking Wizard 6.0 which is connected to the 200MHz differential clock signal (clock_200MHzP (E19 FPGA pin), clock_200MHzN (E18)) and the reset is connected to the RESET signal (AV40) of the Virtex-7 development kit. The synthesizable HW_nMPRA_RTOS implementation integrates a scheduler implemented in hardware to validate excellent performance at a more than the convenient cost in terms of FPGA resources used ( Găitan & Zagan, 2021 ; Zagan & Găitan, 2022 ).…”

“…In Găitan & Zagan (2021) , instructions dedicated to the control of the HW_nMPRA_RTOS integrated scheduling unit are described. Its behavior is controlled via a dedicated instruction set, supporting dynamic interrupt management mechanisms and power-safe functions.…”

“…Table 3 shows the logic for selecting the interrupt event and assigning it to the instPi for preemptive execution. The HW_nMPRA_RTOS registers are described extensively in the processor specification and in Găitan & Zagan (2021) .…”