Hardware realization of a 2D IIR semisystolic filter with application to real-time homomorphic filtering

Kaufman, H.J.; Sid-Ahmed, M.A.

doi:10.1109/76.180686

Cited by 9 publications

(2 citation statements)

References 7 publications

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“…Histogram equalization [ 2 , 3 ], low-light stretching [ 4 ], unsharp masking [ 5 , 6 ], and homomorphic filtering [ 7 , 8 ] are fast-and-straightforward image enhancement techniques. They are highly efficient when the captured scene is slightly hazy because they primarily enhance low-level features such as edges, brightness, and contrast, which significantly influence human perception of image quality.…”

Section: Introductionmentioning

confidence: 99%

Single-Image Visibility Restoration: A Machine Learning Approach and Its 4K-Capable Hardware Accelerator

Ngo

Lee

et al. 2020

Sensors

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In recent years, machine vision algorithms have played an influential role as core technologies in several practical applications, such as surveillance, autonomous driving, and object recognition/localization. However, as almost all such algorithms are applicable to clear weather conditions, their performance is severely affected by any atmospheric turbidity. Several image visibility restoration algorithms have been proposed to address this issue, and they have proven to be a highly efficient solution. This paper proposes a novel method to recover clear images from degraded ones. To this end, the proposed algorithm uses a supervised machine learning-based technique to estimate the pixel-wise extinction coefficients of the transmission medium and a novel compensation scheme to rectify the post-dehazing false enlargement of white objects. Also, a corresponding hardware accelerator implemented on a Field Programmable Gate Array chip is in order for facilitating real-time processing, a critical requirement of practical camera-based systems. Experimental results on both synthetic and real image datasets verified the proposed method’s superiority over existing benchmark approaches. Furthermore, the hardware synthesis results revealed that the accelerator exhibits a processing rate of nearly 271.67 Mpixel/s, enabling it to process 4K videos at 30.7 frames per second in real time.

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Section: Introductionmentioning

confidence: 99%

Single-Image Visibility Restoration: A Machine Learning Approach and Its 4K-Capable Hardware Accelerator

Ngo

Lee

et al. 2020

Sensors

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“…In recent work 34–38, it was shown that a systolic‐array architecture 39–60may be optimized for high temporal throughput by using a 2D look‐ahead (LA) 61–65 method, thereby enabling fast beam PW filtering at a real‐time rate of one‐frame‐per‐clock‐cycle (OFPCC), where a frame is theset of time‐synchronous input spatial samples obtained from the ULA. In 37, 38, 66, it was shown that radio‐frequency (RF) antenna signals may be processed at a rate of OFPCC.…”

Section: Introductionmentioning

confidence: 99%

Massively parallel systolic‐array architectures for 2d IIR polyphase space–time plane‐wave beam digital filters

Madanayake

Gunaratne

Bruton

2010

Circuit Theory & Apps

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SUMMARYA systolic architecture has recently been proposed for implementing two-dimensional infinite impulse response (IIR) space-time beam plane-wave filters at a throughput of one-frame-per-clock-cycle for such applications as real-time broadband smart antennas. A novel polyphase systolic architecture is proposed here that further increases the throughput of these IIR beam filters, by a factor of M, to M-frames-per-clockcycle, where M is the number of polyphases. The proposed method combines the polyphase approach, along with pipelining and look-ahead optimization methods, to achieve frame sample frequencies that are several times higher than the clock-cycle limit of the very large-scale integration (VLSI) technology, thereby potentially allowing multi-GHz frame sample frequencies using current custom VLSI circuits. The implementation of a field programmable gate array-based real-time prototype is described, tested and verified for the two-phase case (M = 2) at a technology-limited clock frequency of 50 MHz which corresponds to a throughput of 100 million-frames-per-clock-cycle.

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A general comparative study of the multiplicative homomorphic, log-ratio and logarithmic image processing approaches

Pinoli

1997

Signal Processing

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Hardware realization of a 2D IIR semisystolic filter with application to real-time homomorphic filtering

Cited by 9 publications

References 7 publications

Single-Image Visibility Restoration: A Machine Learning Approach and Its 4K-Capable Hardware Accelerator

Single-Image Visibility Restoration: A Machine Learning Approach and Its 4K-Capable Hardware Accelerator

Massively parallel systolic‐array architectures for 2d IIR polyphase space–time plane‐wave beam digital filters

A general comparative study of the multiplicative homomorphic, log-ratio and logarithmic image processing approaches

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