Hardware Optimizations of Dense Binary Hyperdimensional Computing: Rematerialization of Hypervectors, Binarized Bundling, and Combinational Associative Memory

Schmuck, Manuel; Benini, Luca; Rahimi, Abbas

doi:10.48550/arxiv.1807.08583

Cited by 2 publications

(2 citation statements)

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“…Its relatively small size makes the timing simulation computationally tractable. We also selected another machine learning algorithm based on computing with hyperdimensional (HD) [49] vectors to detect two face/non-face classes among 10,000 web faces of a face detection dataset (FACE) from Caltech [50]. Fig.…”

Section: Resultsmentioning

confidence: 99%

FPGA Energy Efficiency by Leveraging Thermal Margin

Khaleghi

Salamat

Imani

et al. 2019

2019 IEEE 37th International Conference on Computer Design (ICCD)

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FPGA devices are continuously evolving to meet high computation and performance demand for emerging applications. As a result, cutting edge FPGAs are not energy efficient as conventionally presumed to be, and therefore, aggressive power-saving techniques have become imperative. The clock rate of an FPGA-mapped design is set based on worst-case conditions to ensure reliable operation under all circumstances. This usually leaves a considerable timing margin that can be exploited to reduce power consumption by scaling voltage without lowering clock frequency. There are hurdles for such opportunistic voltage scaling in FPGAs because (a) critical paths change with designs, making timing evaluation difficult as voltage changes, (b) each FPGA resource has particular power-delay trade-off with voltage, (c) data corruption of configuration cells and memory blocks further hampers voltage scaling. In this paper, we propose a systematical approach to leverage the available thermal headroom of FPGA-mapped designs for power and energy improvement. By comprehensively analyzing the timing and power consumption of FPGA building blocks under varying temperatures and voltages, we propose a thermal-aware voltage scaling flow that effectively utilizes the thermal margin to reduce power consumption without degrading performance. We show the proposed flow can be employed for energy optimization as well, whereby power consumption and delay are compromised to accomplish the tasks with minimum energy. Lastly, we propose a simulation framework to be able to examine the efficiency of the proposed method for other applications that are inherently tolerant to a certain amount of error, granting further power saving opportunity. Experimental results over a set of industrial benchmarks indicate up to 36% power reduction with the same performance, and 66% total energy saving when energy is the optimization target.

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Section: Resultsmentioning

confidence: 99%

FPGA Energy Efficiency by Leveraging Thermal Margin

Khaleghi

Salamat

Imani

et al. 2019

2019 IEEE 37th International Conference on Computer Design (ICCD)

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“…In the dense binary coding [16], a letter hypervector has an approximately equal number of randomly placed 1s and 0s, hence the 27 hypervectors are approximately orthogonal to each other. As another alternative, mapping to binary hypervectors can be realized by rematerialization [38] e.g., by using a cellular automaton exhibiting exhibiting chaotic behaviour [39].…”

Section: Mapping and Encoding Modulementioning

confidence: 99%

Hyperdimensional Computing Nanosystem

Rahimi,

Wu,

et al. 2018

Preprint

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One viable solution for continuous reduction in energy-per-operation is to rethink functionality to cope with uncertainty by adopting computational approaches that are inherently robust to uncertainty. It requires a novel look at data representations, associated operations, and circuits, and at materials and substrates that enable them. 3D integrated nanotechnologies combined with novel brain-inspired computational paradigms that support fast learning and fault tolerance could lead the way. Recognizing the very size of the brain's circuits, hyperdimensional (HD) computing can model neural activity patterns with points in a HD space, that is, with hypervectors as large randomly generated patterns. At its very core, HD computing is about manipulating and comparing these patterns inside memory. Emerging nanotechnologies such as carbon nanotube field effect transistors (CNFETs) and resistive RAM (RRAM), and their monolithic 3D integration offer opportunities for hardware implementations of HD computing through tight integration of logic and memory, energy-efficient computation, and unique device characteristics. We experimentally demonstrate and characterize an end-to-end HD computing nanosystem built using monolithic 3D integration of CNFETs and RRAM. With our nanosystem, we experimentally demonstrate classification of 21 languages with measured accuracy of up to 98% on >20,000 sentences (6.4 million characters), training using one text sample (≈100,000 characters) per language, and resilient operation (98% accuracy) despite 78% hardware errors in HD representation (outputs stuck at 0 or 1). By exploiting the unique properties of the underlying nanotechnologies, we show that HD computing, when implemented with monolithic 3D integration, can be up to 420× more energy-efficient while using 25× less area compared to traditional silicon CMOS implementations.

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Hardware Optimizations of Dense Binary Hyperdimensional Computing: Rematerialization of Hypervectors, Binarized Bundling, and Combinational Associative Memory

Cited by 2 publications

References 0 publications

FPGA Energy Efficiency by Leveraging Thermal Margin

FPGA Energy Efficiency by Leveraging Thermal Margin

Hyperdimensional Computing Nanosystem

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