FPGA Energy Efficiency by Leveraging Thermal Margin

Khaleghi, Behnam; Salamat, Sahand; Imani, Mohsen; Rosing, Tajana

doi:10.1109/iccd46524.2019.00059

Cited by 11 publications

(3 citation statements)

References 45 publications

(54 reference statements)

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“…There are also studies for ASIC CNN accelerators [86,132,5]. Following this approach, studies on FPGAbased designs are either fully in simulation [70] or emulation of FPGA netlists on simulation frameworks [45,90]. 8.1.2.…”

Section: Undervoltingmentioning

confidence: 99%

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

Salami¹,

Onural

Yüksel

et al. 2020

2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)

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We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timing faults due to excessive circuit latency increase. We evaluate the reliability-power trade-off for such accelerators. Specifically, we experimentally study the reduced-voltage operation of multiple components of real FPGAs, characterize the corresponding reliability behavior of CNN accelerators, propose techniques to minimize the drawbacks of reduced-voltage operation, and combine undervolting with architectural CNN optimization techniques, i.e., quantization and pruning. We investigate the effect of environmental temperature on the reliability-power trade-off of such accelerators.We perform experiments on three identical samples of modern Xilinx ZCU102 FPGA platforms with five state-of-the-art image classification CNN benchmarks. This approach allows us to study the effects of our undervolting technique for both software and hardware variability. We achieve more than 3X power-efficiency (GOPs/W ) gain via undervolting. 2.6X of this gain is the result of eliminating the voltage guardband region, i.e., the safe voltage region below the nominal level that is set by FPGA vendor to ensure correct functionality in worst-case environmental and circuit conditions. 43% of the power-efficiency gain is due to further undervolting below the guardband, which comes at the cost of accuracy loss in the CNN accelerator. We evaluate an effective frequency underscaling technique that prevents this accuracy loss, and find that it reduces the power-efficiency gain from 43% to 25%.

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Section: Undervoltingmentioning

confidence: 99%

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

Salami¹,

Onural

Yüksel

et al. 2020

2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)

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“…A survey on this topic is presented in [89], considering ultra-low-power techniques for FPGA-based IoT systems. Contributions devoted to improving power consumption on FPGA are presented in [90] and [91].…”

Section: Techniques To Improve Latency Area and Powermentioning

confidence: 99%

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

et al. 2022

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Hardware accelerators based on field programmable gate array (FPGA) and system on chip (SoC) devices have gained attention in recent years. One of the main reasons is that these devices contain reconfigurable logic, which makes them feasible for boosting the performance of applications. High-level synthesis (HLS) tools facilitate the creation of FPGA code from a high level of abstraction using different directives to obtain an optimized hardware design based on performance metrics. However, the complexity of the design space depends on different factors such as the number of directives used in the source code, the available resources in the device, and the clock frequency. Design space exploration (DSE) techniques comprise the evaluation of multiple implementations with different combinations of directives to obtain a design with a good compromise between different metrics. This paper presents a survey of models, methodologies, and frameworks proposed for metric estimation, FPGA-based DSE, and power consumption estimation on FPGA/SoC. The main features, limitations, and trade-offs of these approaches are described. We also present the integration of existing models and frameworks in diverse research areas and identify the different challenges to be addressed. INDEX TERMSComputing models, design space exploration, field programmable gate array (FPGA), system on chip (SoC), power consumption.years (2016-2022) and have been selected based on the topics addressed in this survey. Several papers published before 2016 have been considered because of their contributions to the current literature. C. OUTLINEThe remainder of this paper is organized as follows. Section II briefly presents the most widely used parallel computing models for CPU, GPU, and multicore processors. Section III introduces the FPGA-based reconfigurable hardware accelerator architectures, hardware/software co-design, DSE and metrics, and the techniques to improve latency, area, and power for this technology. In Section IV, we describe previous works on models, methodologies, and frameworks proposed for FPGA/SoC according to their main features: metrics estimation (IV-A), FPGA-based DSE (IV-B), and power consumption estimation (IV-C); and in Section IV-D, we present a summary and discussion. The integration of models and frameworks for FPGA-based reconfigurable hardware accelerators in different research fields is exposed in Section V. Challenges are analyzed in Section VI. Finally, conclusions are presented in Section VII. II. PARALLEL COMPUTING MODELS FOR PERFORMANCE ESTIMATIONComputing models allow to easily analyzing algorithms by simplifying the computational world to a reduced set of parameters that define the cost of arithmetic and memory access operations and communication. These models contribute to the search for efficient algorithms for a given architecture, improving the productivity of designers, programmers, and engineers. A small amount of communication, a small number of operations, and a high degree of parallelism are key points that d...

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“…A thermal-aware voltage scaling has been proposed in [22]. Voltage selection algorithm has been developed and integrated within FPGA synthesis process to aggressively scale the core and block RAM voltages, utilizing the available thermal headroom of the FPGA-mapped design.…”

Section: Prior and Related Workmentioning

confidence: 99%

A Machine Learning Pipeline Stage for Adaptive Frequency Adjustment

Ajirlou

Partin-Vaisband

2022

IEEE Trans. Comput.

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A machine learning (ML) design framework is proposed for adaptively adjusting clock frequency based on propagation delay of individual instructions. A random forest model is trained to classify propagation delays in real time, utilizing current operation type, current operands, and computation history as ML features. The trained model is implemented in Verilog as an additional pipeline stage within TigerMIPS processor. The modified system is experimentally tested at the gate level in 45 nm CMOS technology, exhibiting simultaneously a speedup of 70% and an energy reduction of 30% with coarse-grained ML classification as compared with the baseline TigerMIPS. A speedup of 89% is demonstrated with finer granularities with a simultaneous 15.5% reduction in energy consumption.

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FPGA Energy Efficiency by Leveraging Thermal Margin

Cited by 11 publications

References 45 publications

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

A Machine Learning Pipeline Stage for Adaptive Frequency Adjustment

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