Hardware Implementation on Field Programmable Gate Array of Two-Stage Algorithm for Rough Set Reduct Generation

Grzes, Tomasz; Kopczynski, Maciej

doi:10.1007/978-3-030-22815-6_38

Cited by 4 publications

(1 citation statement)

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“…Previous authors' research results focused on the subject of hardware implementations of rough sets methods can be found in previously published papers: the idea of the processor for rough sets methods [25], hardware-supported reduct calculation [10], the first approach to core generation using FPGA based solution [11], hardware unit for processing datasets consisting of millions of objects [12], a two-stage algorithm for finding reduct [5] as well as finding minimal reduct with two FPGA devices [2]. This paper is a new proposition for parallel hardware supported core calculation for big datasets and introduces modification of methods described in [11] and [13].…”

Section: Introductionmentioning

confidence: 99%

Hardware Rough Set Processor Parallel Architecture in FPGA for Finding Core in Big Datasets

Kopczynski

Grzes

2021

Journal of Artificial Intelligence and Soft Computing Research

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This paper presents FPGA and softcore CPU based solution for large datasets parallel core calculation using rough set methods. Architectures shown in this paper have been tested on two real datasets running presented solutions inside FPGA unit. Tested datasets had 1 000 to 10 000 000 objects. The same operations were performed in software implementation. Obtained results show the big acceleration in computation time using hardware supporting core generation in comparison to pure software implementation.

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