Hardware implementation of all digital calibration for undersampling TIADCs

Duc, Han Le; Nguyen, Duc Minh; Jabbour, Chadi; Graba, Tarik; Desgreys, Patricia; Jamin, Olivier; Nguyen, Van Tam

doi:10.1109/iscas.2015.7169113

Cited by 23 publications

(8 citation statements)

References 12 publications

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“…The literature review depicts that foreground and background calibrations constitute the basis of different techniques for the correction of timing skew error. Moreover, careful investigation over the last decade demonstrates that most of the reported works pertain to background calibration 8–12 because it is not necessary to take the ADC offline for the calibration process 2 . The common feature of all architectures that utilize this procedure lies in the exploitation of a statistical‐based approach.…”

Section: Introductionmentioning

confidence: 99%

Effective extraction method for triple errors in foreground calibration of TI‐ADCs

Azizian

Ehsanian

2021

Circuit Theory & Apps

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This paper presents a novel procedure for detecting offset, gain, and timing skew errors in foreground calibration of time-interleaved analog-to-digital converters (TI-ADCs). An efficient peak detection scheme has been introduced, which is successfully employed to extract timing skew error. The designed method has also been extended to derive the gain and offset errors separately to form the generalized architecture. The objective is performed with the adjustment of the rational coefficient for each error. Simplicity and low hardware consumption will constitute the notable advantages of the proposed algorithm. Mathematical expressions have been provided to explain the principles.A special case in which all triple errors could exist together has also been analyzed. Then, the proposed architecture was implemented at the system level. Finally, the behavioral simulation results for a 12-bit four-channel TI-ADC have been demonstrated to confirm the accuracy of the proposed algorithm. The simulation environment has consisted of the sampling frequency of 8 GHz for TI-ADC and 1 GHz single-tone input frequency for each channel (associated with the Gaussian noise). Based on the results, the maximum value of 77.21 dB for SFDR has been achieved after the calibration process when the average error of 9% for timing skew and 6% tolerance for gain were considered for the channels of TI-ADC.

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Section: Introductionmentioning

confidence: 99%

Effective extraction method for triple errors in foreground calibration of TI‐ADCs

Azizian

Ehsanian

2021

Circuit Theory & Apps

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“…Ref. [18] utilizes zero-crossing in the compensated signal and image signal, which is heavily dependent on statistics input. Ref.…”

Section: Introductionmentioning

confidence: 99%

A channel multiplexing digital calibration technique for timing mismatch of time-interleaved ADCs

Yin

Liu

Chen

et al. 2019

IEICE Electron. Express

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This paper presents an all-digital calibration technique for timeinterleaved ADC (TIADC) timing mismatch. The calibration architecture is based on a channel multiplexing architecture. For a M-channel TIADC, only one centralized calibration module is needed. Timing mismatches between channels are estimated by correlating the adjacent channel's outputs and a compensation algorithm based on the one-order five-point differentiator is employed to suppress the mismatches. Compared with conventional parallel calibration architecture, the proposed calibration architecture works well in higher Nyquist bands (NB) with high-scalability. The hardware consumption does not increase linearly with the number of sub-ADCs.

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“…The performance of such type of calibration techniques can be studied in advance through simulations and/or analysis. Due to the ease of implementation and significant performance improvement, these techniques have become popular and as a result, researchers have proposed various types of such techniques [17][18][19][20][21][22][23][24][25][26][27][28][29]. However, there is no single fully digital calibration technique that can replace all the other techniques, because the performances of the fully digital calibration techniques vary under different conditions.…”

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confidence: 99%

“…However, there is no single fully digital calibration technique that can replace all the other techniques, because the performances of the fully digital calibration techniques vary under different conditions. There are 2020 JINST 15 P01024 several limitations of fully digital calibration techniques, such as the requirement of an additional reference ADC [18,19], the analog input to be located in the first Nyquist band (NB) [20][21][22][23][24], and the limit on the number of sub-ADC channels [25][26][27][28]. Therefore, fully digital calibration techniques should be explored further to overcome these limitations.…”

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confidence: 99%

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Low computing resource consumption fully digital foreground calibration technique for time-interleaved analog-to-digital converter

Cao

Liu

et al. 2020

J. Inst.

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A time-interleaved analog-to-digital converter (TI-ADC) uses several sub-analog-todigital converters (sub-ADCs) to achieve a high sampling rate. Its applications include communication systems, oscilloscopes, healthcare instruments, etc. However, the presence of sub-ADC channel mismatches such as offset, gain and sample-time mismatches can significantly degrade the performance of TI-ADCs. This paper proposes a fully digital foreground calibration technique for the TI-ADC, including mismatch correction and estimation blocks. Unlike existing techniques, the proposed technique requires low computational resources. As the resource for complex computing in a field-programmable gate array (FPGA) is mainly the digital signal processor (DSP), the mismatch correction block unifies each computing unit in the FPGA into a multiply adder to achieve low DSP consumption. To further reduce the use of DSP resources, the selection of an optimal number of taps of the finite impulse response filter used for mismatch correction is discussed. The optimal-tap filter that uses the lowest amount of DSPs while satisfying the required signal-to-noise and distortion ratio flat area bandwidth is presented. A real-time hardware correction block was implemented for an 8 Gs/s TI-ADC system with two sub-ADC channels, and the results with this hardware verify the low computing resource consumption feature of the proposed calibration technique.

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Hardware implementation of all digital calibration for undersampling TIADCs

Cited by 23 publications

References 12 publications

Effective extraction method for triple errors in foreground calibration of TI‐ADCs

Effective extraction method for triple errors in foreground calibration of TI‐ADCs

A channel multiplexing digital calibration technique for timing mismatch of time-interleaved ADCs

Low computing resource consumption fully digital foreground calibration technique for time-interleaved analog-to-digital converter

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