IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society 2018
DOI: 10.1109/iecon.2018.8591409
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Hardware-Efficient Velocity Estimation of Dynamic Obstacles Based on a Novel Radix-4 CORDIC and FPGA Implementation

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Cited by 3 publications
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“…However, this method resulted in many iterations and a long delay. In [33][34][35], the authors proposed a highradix CORDIC algorithm to reduce delay, but the hardware circuit structure was complex and difficult to implement. To solve this problem, the authors of [36] proposed a greedy CORDIC algorithm which greatly reduced the usage of RAM resources and improved real-time performance.…”
Section: Introductionmentioning
confidence: 99%
“…However, this method resulted in many iterations and a long delay. In [33][34][35], the authors proposed a highradix CORDIC algorithm to reduce delay, but the hardware circuit structure was complex and difficult to implement. To solve this problem, the authors of [36] proposed a greedy CORDIC algorithm which greatly reduced the usage of RAM resources and improved real-time performance.…”
Section: Introductionmentioning
confidence: 99%