Hardware‐efficient slope‐error algorithm based PAM4 baud rate CDR scheme for 40 Gb/s receiver

Abstract

A hardware-efficient slope-error (SE) algorithm based four-level pulse amplitude modulation (PAM4) baud rate clock and data recovery (CDR) scheme is proposed. The algorithm uses three adjacent data information to obtain slope information, thus reduces the required error samplers by 75% compared to the widely used baud rate CDR, namely, Mueller Müller (MM) CDR when working at same phase detector (PD) gain. The power efficiency of the CDR loop is improved by 36% compared to MM CDR. The proposed PAM4 baud rate CDR does not bring in extra block except for PD, which makes it easy to be extended from adaptive decision feedback equalisation. A 40 Gb/s PAM4 receiver with the proposed CDR is designed in 55 nm CMOS process. The simulated jitter tolerance of the CDR at high frequency exceeds the SONET OC-768 JTOL mask by at least 0.35 UI at the bit error rate of 10 −12. The CDR loop consumes 106 mW from a 1.2 V supply and occupies an active area of 0.1 mm 2 .

Hybrid Timing Error Detector for Baud Rate Multilevel Clock and Data Recovery

“…For the minimum mean square error (MMSE) based phase detector, analog filters are required to extract the error signal and slope using the same clock signal [1]. An alternative to the filter approach is to use a pair of closely spaced clock phases around the baud rate clock to extract the slope [2]. This results in local clock generation complexity similar to the oversampled PDs.…”

Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model

“…The baud-rate CDR only collects one sample per unit interval (UI), so the rate requirement of sampling clock is halved compared with the Bang-Bang PD. Baud rate CDR usually adopts Mueller-Muller phase detector (MMPD) to determine the best sampling phase of the ADC clock [1][2][3].…”

“…The baud-rate CDR only collects one sample per unit interval (UI), so the rate requirement of sampling clock is halved compared with the Bang-Bang PD. Baud rate CDR usually adopts Mueller-Muller phase detector (MMPD) to determine the best sampling phase of the ADC clock [1][2][3].The intuitive understanding of the performance of the CDR loop is whether it can provide an optimal sampling phase for the ADC to make the wireline transceiver system achieve the lowest bit error rate (BER). In the testing stage, we can obtain the performance of the CDR through the BER results, however, in simulation, it is hard for us to verify the communication protocol's requirements for BER of 10 -12 or even 10 -15 .…”

A High Phase Detection Density and Low Space Complexity Mueller-Muller Phase Detector for DB PAM-4 Wireline Receiver

“…The phase information extraction of conventional CDR relies on the Bang-Bang (BB) phase-detection technique [5][6][7], which requires two samples 1 unit interval (UI) to obtain variable edge information and data information in turn, and requires high sampler bandwidth. Using Mueller-Muller (MM) phase-detection technique [8][9][10][11], with only sample 1 UI, reducing the sampler bandwidth requirement and the amount of data processing. The original structure of the sampler plus CDR for Data Retiming under pam-4 modulation [11][12][13] is not applicable to the current modulation mode.…”