Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC

Han, Donghyun; Lee, Youngkwang; Lee, Sooryeong; Kang, Sungho

doi:10.1109/isocc53507.2021.9613959

“…However, each TSV has its test circuit which causes a large area and power overhead. The authors of [24] showed that testing of 3D-SICs is a challenge due to their complex structure. After stacking, the power and ground TSVs are connected to a grid that makes their testing a challenging task.…”

Section: Related Workmentioning

confidence: 99%

Approximate TSV-based 3D Stacked Integrated Circuits by Inexact Interconnects

Masadeh¹

2022

IJACSA

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Three-Dimensional Stacked Integrated Circuit (3D-SICs) based on Through-Silicon Vias (TSVs) provide a highdensity integration technology. However, integrating pre-tested dies requires post-bond interconnect testing, which is complex and costly. An imperfect TSV-based interconnect indicates a defective chip that should be rejected. Thus, it increases the yield loss and test cost. On the other hand, approximate computing (AC) is a promising design paradigm suitable for errorresilient applications, e.g., processing sensory-generated data, by judiciously sacrificing output accuracy. AC perform inexact operations and accepts inexact data. Thus, introducing AC into 3D-SICs will significantly ameliorate the efficiency of design approximation. Therefore, this work aims to increase the yield and reduce the test cost by accepting 3D-SICs with defected interconnects as approximate 3D-SICs. This work considers 3D-SICs, where the sensor is stacked on logic (CPU) which is stacked on memory (DRAM). Then, use the memory-based interconnect testing (MBIT) approach to detect and diagnose the faulty interconnect. Based on the detected fault location and type, and for a maximum allowed error, some sensory 3D-SICs with defected LSBs interconnects are accepted and used in errorresilient and data-intensive applications. Targeting data lines only, 50% of the defected interconnects, i.e., least significant bits (LSBs), were accepted as approximate. Thus, the proposed work was able to significantly increase the yield. Two applications, i.e., ECG signal compression and detecting of their R peaks, demonstrated the effectiveness of using a sensory device with a faulty data line in its least significant 8-bits. The approximate ECG signals have a compression rate higher than the exact with negligible (around 0.1%) reduced accuracy.

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2D/2.5D/3D Heterogeneous Integration

Endrinal,

Huat

2023

Electronic Device Failure Analysis Technology Roadmap

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Recent trends in electronic packaging, including the growing use of 3D designs and heterogeneous integration, are greatly adding to the complexity of isolating faults in semiconductor products. This chapter reviews the latest IC packaging and integration solutions and assesses the readiness level of fault isolation tools and techniques. It examines the capabilities, limitations, and optimization potential of x-ray tomography and magnetic field imaging, describes various approaches for optical fault isolation, and compares and contrasts pre-OFI sample preparation methods. The chapter also explains how time-domain and electro-optical terahertz pulse reflectometry are used to find shorts and opens in ICs and how challenges related to heterogenous integration may be met through design for testability (DFT) and built-in self-test (BIST) accommodations and the use of passive interposers.

show abstract

2D/2.5D/3D Heterogeneous Integration

Endrinal,

Huat

2023

Electronic Device Failure Analysis Technology Roadmap

0

View full text Add to dashboard Cite

Recent trends in electronic packaging, including the growing use of 3D designs and heterogeneous integration, are greatly adding to the complexity of isolating faults in semiconductor products. This chapter reviews the latest IC packaging and integration solutions and assesses the readiness level of fault isolation tools and techniques. It examines the capabilities, limitations, and optimization potential of x-ray tomography and magnetic field imaging, describes various approaches for optical fault isolation, and compares and contrasts pre-OFI sample preparation methods. The chapter also explains how time-domain and electro-optical terahertz pulse reflectometry are used to find shorts and opens in ICs and how challenges related to heterogenous integration may be met through design for testability (DFT) and built-in self-test (BIST) accommodations and the use of passive interposers.

show abstract

Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC

Cited by 3 publications

References 5 publications

Approximate TSV-based 3D Stacked Integrated Circuits by Inexact Interconnects

Approximate TSV-based 3D Stacked Integrated Circuits by Inexact Interconnects

2D/2.5D/3D Heterogeneous Integration

2D/2.5D/3D Heterogeneous Integration

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