Hardware Design and Realization for Iteratively Decodable Codes

2016 Euromicro Conference on Digital System Design (DSD)

Gupta

Pezzin

et al. 2016

International audience—In this paper, we propose a layered LDPC decoder architecture targeting flexibility, high-throughput, low cost, and efficient use of the hardware resources. The proposed architecture provides full design time flexibility, i.e., it can accommodate any Quasi-Cyclic (QC) LDPC code, and also allows redefining a number of parameters of the QC-LDPC code at the run time. The main novelty of the paper consists of: (1) a new low-cost processing unit that merges in an efficient way the logical functionalities of the Variable-Node Unit (VNU) and the A Posteriori Log-Likelihood Ratio (AP-LLR) unit, (2) a high speed, low-cost Check-Node Unit (CNU) architecture, which is executed twice in order to complete the computation of the check-node messages at each iteration, (3) a splitting of the iteration processing in two perfectly symmetric stages, executed in two consecutive clock cycles, each one using exactly the same processing resources; the processing load is perfectly balanced between the two clock cycles, thus yielding an optimal clock frequency. Synthesis results targeting a 65nm CMOS technology for a (3, 6)-regular (648, 1296) Quasi-Cyclic LDPC code and for the WiMax (1152, 2304) irregular QC-LDPC code show significant improvements in terms of area and throughput compared to the baseline architecture discussed in this paper, as well as several state of the art implementations

mentioning

confidence: 85%

Section: Introductionmentioning

confidence: 99%

Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units

2016 Euromicro Conference on Digital System Design (DSD)

Gupta

Pezzin

et al. 2016

“…When F is applied at the VNprocessing step, both VN-and CN-messages belong to a strict subset of the alphabet M, namely M ′ = Im(F ) ⊂ M. This may result in significant memory savings for storing the exchanged messages. It is worth noting that many hardware implementations of Quasi-Cyclic (QC) LDPC decoders rely on a layered architecture, which only requires storing the checknode messages [12].…”

Section: Implementation Benefitsmentioning

confidence: 99%

Non-surjective finite alphabet iterative decoders

2016 IEEE International Conference on Communications (ICC)

Savin

et al. 2016

International audienceThis paper introduces a new theoretical framework, akin to the use of imprecise message storage in Low Density Parity Check (LDPC) decoders, which is seen as an enabler for cost-effective hardware designs. The proposed framework is the one of Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), and it is shown to provide a unified approach for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for WiMAX irregular LDPC codes and we show they provide different trade-offs between hardware complexity and decoding performance. In particular, we derive a set of 27 NS-FAIDs that provide decoding gains up to 0.36 dB, while yielding a memory / interconnect reduction up to 25% / 30% compared to the Min-Sum decoder

“…When F is applied at the VN-processing step, both VN-and CN-messages belong to a strict subset of the alphabet M, namely M = Im(F ) ⊂ M. When F is applied at the CN-processing step, only CN-messages belong to M . However, it is worth noting that many hardware implementations of Quasi-Cyclic (QC) LDPC decoders rely on a layered architecture, which only requires storing the checknode messages [7].…”

Section: Examples Of Ns-faidsmentioning

confidence: 99%

“…One important characteristic of LDPC decoders is that the memory and interconnect blocks dominate the overall area/delay/power performance of the hardware design [7]. To address this issue, we build upon the concept of Finite Alphabet Iterative Decoders (FAIDs), introduced in [8]- [10].…”

Section: Introductionmentioning

confidence: 99%

Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders

Savin

et al. 2018

IEEE Trans. VLSI Syst.

Abstract-This paper introduces a new approach to costeffective, high-throughput hardware designs for Low Density Parity Check (LDPC) decoders. The proposed approach, called Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), exploits the robustness of message-passing LDPC decoders to inaccuracies in the calculation of exchanged messages, and it is shown to provide a unified framework for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for regular and irregular LDPC codes, and are shown to provide different trade-offs between hardware complexity and decoding performance. Two hardware architectures targeting high-throughput applications are also proposed, integrating both Min-Sum (MS) and NS-FAID decoding kernels. ASIC post synthesis implementation results on 65nm CMOS technology show that NS-FAIDs yield significant improvements in the throughput to area ratio, by up to 58.75% with respect to the MS decoder, with even better or only slightly degraded error correction performance.