Hardware design and implementation of a novel ANN-based chaotic generator in FPGA

Alçın, Murat; Pehlivan, İ̇hsan; Koyuncu, İ̇smail

doi:10.1016/j.ijleo.2016.03.042

Cited by 78 publications

(41 citation statements)

References 10 publications

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“…22 tests. 17 It should be noted that some preliminary results of this new technique in the context of design and implementation of ANN-based chaotic generator on FPGA has been previously reported by Alçın et al 18 ; however, in the present paper, novel high-speed TRNG, as well as more general and conclusive results, has been additionally presented using this chaotic generator in Alçın et al 18 .…”

Section: Introductionmentioning

confidence: 65%

“…As mentioned above, implementation of ANN-based chaotic generator on FPGA has been previously reported by Alçın et al 18 including offline training step and preprocessing step; however, in the present paper, a novel high-speed TRNG, as well as more general and conclusive results, has been designed and realized using the outputs of the ANN-based chaotic generator on FPGA.…”

Section: The Design and Realization Of Ann-based Trng On Fpgamentioning

confidence: 96%

“…ANN‐based PUCS Oscillator component (APOC) has been previously reported on Alçın et al The quantification component consists of three number generators (X‐number generator, Y‐number generator, and Z‐number generator), a multiplexer (MUX), and a counter unit. The number generators consist of signals namely Output_X, Output_Y and Output_Z which have been received from APOC and Ready_X, Ready_Y, and Ready_Z .…”

Section: The Design and Realization Of Ann‐based Trng On Fpgamentioning

confidence: 99%

“…ANN-based PUCS Oscillator component (APOC) has been previously reported on Alçın et al 18 The quantification component consists of three number generators (X-number generator, Y-number generator, and Z-number The signals namely Ready_X, Ready_Y, and Ready_Z are the control signals of Output_X, Output_Y, and Output_Z, respectively. Since the least significant bit of the number in the fraction section (b 0 ) is the most precise bit with high bit encoding, b 0 can be changed even when a slight alteration occurs.…”

Section: The Design and Realization Of Ann-based Trng On Fpgamentioning

confidence: 99%

See 3 more Smart Citations

A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

Alçın

Koyuncu

Tuna

et al. 2018

Circuit Theory & Apps

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Summary It is well observed that cryptographic applications have great challenges in guaranteeing high security as well as high throughput. Artificial neural network (ANN)–based chaotic true random number generator (TRNG) structure has not been unprecedented in current literature. This paper provides a novel type of high‐speed TRNG based on chaos and ANN implemented in a Xilinx field‐programmable gate array (FPGA) chip. The paper consists of two main parts. In the first part, chaos analyses of Pehlivan‐Uyaroglu_2010 chaotic system (PUCS) have been accomplished to prove that PUCS operates in chaotic regime. So PUCS can be an efficient alternative to the entropy source for classical TRNGs. In the second part, the hardware design of the proposed TRNG has been created using VHDL in Xilinx platform. As a result, the implemented TRNG offers throughput up to 115.794 Mbps. Besides, the generated random numbers have been tested with the FIPS 140‐1 and NIST 800.22 test suites. The high quality of generated true random numbers have been confirmed by passing all randomness tests. The results have shown that the proposed system can provide not only high throughput but also high quality random bit sequences for a wide variety of embedded cryptographic applications.

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Section: Introductionmentioning

confidence: 65%

Section: The Design and Realization Of Ann-based Trng On Fpgamentioning

confidence: 96%

Section: The Design and Realization Of Ann‐based Trng On Fpgamentioning

confidence: 99%

Section: The Design and Realization Of Ann-based Trng On Fpgamentioning

confidence: 99%

See 2 more Smart Citations

A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

Alçın

Koyuncu

Tuna

et al. 2018

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…In [4] proposed a hardware implementation of ANN-based chaotic generator in FPGA. The chaotic generator was reconstructed by the Feed Forward Neural Network (FFNN), which was created using MATLAB.…”

Section: Related Workmentioning

confidence: 99%

High speed numerical integration algorithm using FPGA

Razak¹,

Talip²,

Yakub³

et al. 2018

J. Fundam and Appl Sci.

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Conventionally, numerical integration to accomplish. Field Programmable Gate Arrays (FPGAs) can be used as a efficient and reliable alternative to implement the proposed a hardware implementation of four numerical integration algorithms using FPGA. The computation is based on Left Riemann Sum (LRS), Right Riemann Sum (RRS), MiddleRiemann Sum (MRS) and Trapezoidal Sum (TS) algorithms. The system performance is evaluated based on target chip Altera Cyclone IV FPGA in the metrics of resources utilization, clock latency, execution time, power consumption and computational error compared to the other algorithms. The result also shows execution time of the FPGA are much faster compared to the software implementation.

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