Hardware coprocessors for high-performance symmetric cryptography

High throughput and area‐efficient FPGA implementation of AES for high‐traffic applications

“…As a result, although the design in [25] occupied a few LUTs, it is not suitable for encrypting sequential and dependent large data, such as images. Although the method proposed in [13] was implemented in different FPGAs, it is pipelined with CTR mode, which is very similar to our work. As is observed from Table 2, the proposed design has the highest throughput, 79.7 Gbps.…”

“…The experiments performed in [5, 13, 23] are in CTR mode. In [5], four 128‐bit AES cores are executed in parallel; as the authors of [5] have mentioned that the throughput of a single core is a quarter of their four designs, the throughput for one core is equal to 44.7 Gbps.…”

“…AESs based on co‐processor and specific processor are implemented [9–12]. The authors of [13] described pipelined implementations of AES and International Data Encryption Algorithm (IDEA), the other symmetric cryptography algorithm, with CTR mode and LUT for Sub‐Bytes on FPGA. In [5], different pipelined AES implementations in ECB and CTR mode by using combinational logic circuits and the simplified of the S‐box were presented.…”