High throughput and area‐efficient FPGA implementation of AES for high‐traffic applications

Shahbazi, Karim; Ko, Seok‐Bum

doi:10.1049/iet-cdt.2019.0179

Cited by 25 publications

(18 citation statements)

References 28 publications

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“…A comparison of the AES-FJMKE architecture is presented in this section. In this research, six different existing methods, namely AES-PNSG [41], AES-AT [42], typical AES [43], AES-BE [43], ISAES [44], AES-RS [45], and AES-MPPRM [46], are used to evaluate the AES-FJMKE architecture. Here, the evaluation is performed using six FPGA devices such as Virtex 4, Virtex 5, Virtex 6, Spartan 3, Spartan 6, and Kintex 7.…”

Section: Comparative Evaluationmentioning

confidence: 99%

“…Tables 8-13 shows the evaluation of the AES-FJMKE with AES-PNSG [41], AES-AT [42], typical AES [43], AES-BE [43], ISAES [44], AES-RS [45], and AES-MPPRM [46], respectively. Tables 8-13 compare the data of Virtex 4, Virtex 5, Virtex 6, Spartan 3, Spartan 6, and Kintex 7, respectively.…”

Section: Comparative Evaluationmentioning

confidence: 99%

Section: Comparative Evaluationmentioning

confidence: 99%

“…The reasons for the poor performance of existing architectures are specified as follows: the AES-PNSG [41] requires higher hardware resources, because of the non-pipelined stages-based AES implementation. Next, the AES-AT [42], AES-BE [43], and ISAES [44] have resulted in a high delay while encrypting and decrypting the plain texts. Further, the design of AES-MPPRM [46] requires a frequent computation of secret keys to accomplish encryption/decryption processes, which increases the hardware resources of the overall AES.…”

Section: Comparative Evaluationmentioning

confidence: 99%

“…However, the design of AES using non-pipelined stages required high hardware resources. Shahbazi and Ko [42] presented the 128-bit of AES in counter mode for high traffic applications. Inner and outer pipelining methods were used to achieve high throughput, and an affine transformation (AT) method was designed to minimize the area.…”

Section: Introductionmentioning

confidence: 99%

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Implementation of Speed-Efficient Key-Scheduling Process of AES for Secure Storage and Transmission of Data

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Balmuri²,

Marchewka

et al. 2021

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Nowadays, a large number of digital data are transmitted worldwide using wireless communications. Therefore, data security is a significant task in communication to prevent cybercrimes and avoid information loss. The Advanced Encryption Standard (AES) is a highly efficient secure mechanism that outperforms other symmetric key cryptographic algorithms using message secrecy. However, AES is efficient in terms of software and hardware implementation, and numerous modifications are done in the conventional AES architecture to improve the performance. This research article proposes a significant modification to the AES architecture’s key expansion section to increase the speed of producing subkeys. The fork–join model of key expansion (FJMKE) architecture is developed to improve the speed of the subkey generation process, whereas the hardware resources of AES are minimized by avoiding the frequent computation of secret keys. The AES-FJMKE architecture generates all of the required subkeys in less than half the time required by the conventional architecture. The proposed AES-FJMKE architecture is designed and simulated using the Xilinx ISE 5.1 software. The Field Programmable Gate Arrays (FPGAs) behaviour of the AES-FJMKE architecture is analysed by means of performance count for hardware resources, delay, and operating frequency. The existing AES architectures such as typical AES, AES-PNSG, AES-AT, AES-BE, ISAES, AES-RS, and AES-MPPRM are used to evaluate the efficiency of AES-FJMKE. The AES-FJMKE implemented using Spartan 6 FPGA used fewer slices (i.e., 76) than the AES-RS.

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