Hardware Coprocessor Synthesis from an ANSI C Specification

Ahuja, Sumit; Gurumani, Swathi; Spackman, C.; Shukla, Sandeep K.

doi:10.1109/mdt.2009.81

Cited by 17 publications

(32 citation statements)

References 4 publications

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“…The process of creating hardware accelerators from C2R, covered in [11], requires adding explicit statements to handle concurrency and manual application of loop unrolling to enable better pipelining. The ROCCC 2.0 compiler system requires no annotations to the C source in order to generate efficient pipelined hardware.…”

Section: Related Workmentioning

confidence: 99%

Designing Modular Hardware Accelerators in C with ROCCC 2.0

Villarreal¹,

Park²,

Najjar

et al. 2010

2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines

155

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Abstract-While FPGA-based hardware accelerators have repeatedly been demonstrated as a viable option, their programmability remains a major barrier to their wider acceptance by application code developers. These platforms are typically programmed in a low level hardware description language, a skill not common among application developers and a process that is often tedious and error-prone. Programming FPGAs from high level languages would provide easier integration with software systems as well as open up hardware accelerators to a wider spectrum of application developers.In this paper, we present a major revision to the Riverside Optimizing Compiler for Configurable Circuits (ROCCC) designed to create hardware accelerators from C programs. Novel additions to ROCCC include (1) intuitive modular bottom-up design of circuits from C, and (2) separation of code generation from specific FPGA platforms. The additions we make do not introduce any new syntax to the C code and maintain the high level optimizations from the ROCCC system that generate efficient code. The modular code we support functions identically as software or hardware. Additionally, we enable user control of hardware optimizations such as systolic array generation and temporal common subexpression elimination.We evaluate the quality of the ROCCC 2.0 tool by comparing it to hand-written VHDL code. We show comparable clock frequencies and a 18% higher throughput. The productivity advantages of ROCCC 2.0 is evaluated using the metrics of lines of code and programming time showing an average of 15x improvement over hand-written VHDL.

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Section: Related Workmentioning

confidence: 99%

Designing Modular Hardware Accelerators in C with ROCCC 2.0

Villarreal¹,

Park²,

Najjar

et al. 2010

2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines

155

View full text Add to dashboard Cite

show abstract

“…As iniciativas na área abordam o problema das mais variadas formas, com diferentes propósitos e aplicações. O objetivo pode ser a construção de sistemas completos, inclusive realizando o co-projeto de software/hardware, ou partes de sistemas como aceleradores e coprocessadores (Ahuja et. al., 2009).…”

Section: Considerações Finaisunclassified

LALP: uma linguagem para exploração do paralelismo de loops em computação reconfigurável

Menotti¹

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Aos meus pais, José e Elda, pelo carinho, dedicação e pelas orações. Aos meus irmãos Rodrigo e Regiane, pelo apoio em todos os momentos. À Ana Rubia, pelo incentivo e compreensão. Aos meus orientadores, professor Eduardo Marques e professor João Cardoso da FEUP, pelo apoio, confiança, orientações acadêmicas e pessoais, e pela amizade. Ao professor Marcio Fernandes da UFSCar, pela ajuda nos trabalhos realizados em cooperação. Ao professor João Lima da UAlg, pelo companheirismo e pela acolhida no Algarve.

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“…However, HLS has been used to optimize implementations of the cryptography protocols in hardware [8,11]. There are few works that uses HLS to implement the AES algorithm on FPGAs [1,9,12,18].…”

Section: Related Workmentioning

confidence: 99%

“…In [1], authors investigated various optimizations of the C-based AES implementation into hardware using C2R [3] methodology for co-processor synthesis. These implementations included baseline hardware design, BRAM-based architecture, a pipelined scheme, and an optimized architecture for performance and area.…”

Section: Related Workmentioning

confidence: 99%

Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS)

Daoud

Hussein

Rafla

EPiC Series in Computing

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Advanced Encryption Standard (AES) represents a fundamental building module of many network security protocols to ensure data confidentiality in various applications ranging from data servers to low-power hardware embedded systems. In order to optimize such hardware implementations, High-Level Synthesis (HLS) provides flexibility in designing and rapid optimization of dedicated hardware to meet the design constraints. In this paper, we present the implementation of AES encryption processor on FPGA using Xilinx Vivado HLS. The AES architecture was analyzed and designed by loop unrolling, and inner-round and outer-round pipelining techniques to achieve a maximum throughput of the AES algorithm up to 1290 Mbps (Mega bit per second) with very significant low resources of 3.24% slices of the FPGA, achieving 3 Mbps per slice area.

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Hardware Coprocessor Synthesis from an ANSI C Specification

Cited by 17 publications

References 4 publications

Designing Modular Hardware Accelerators in C with ROCCC 2.0

Designing Modular Hardware Accelerators in C with ROCCC 2.0

LALP: uma linguagem para exploração do paralelismo de loops em computação reconfigurável

Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS)

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