Designing Modular Hardware Accelerators in C with ROCCC 2.0

Abstract

Abstract-While FPGA-based hardware accelerators have repeatedly been demonstrated as a viable option, their programmability remains a major barrier to their wider acceptance by application code developers. These platforms are typically programmed in a low level hardware description language, a skill not common among application developers and a process that is often tedious and error-prone. Programming FPGAs from high level languages would provide easier integration with software systems as well as open up hardware accelerators to a wider spectrum of application developers.In this paper, we present a major revision to the Riverside Optimizing Compiler for Configurable Circuits (ROCCC) designed to create hardware accelerators from C programs. Novel additions to ROCCC include (1) intuitive modular bottom-up design of circuits from C, and (2) separation of code generation from specific FPGA platforms. The additions we make do not introduce any new syntax to the C code and maintain the high level optimizations from the ROCCC system that generate efficient code. The modular code we support functions identically as software or hardware. Additionally, we enable user control of hardware optimizations such as systolic array generation and temporal common subexpression elimination.We evaluate the quality of the ROCCC 2.0 tool by comparing it to hand-written VHDL code. We show comparable clock frequencies and a 18% higher throughput. The productivity advantages of ROCCC 2.0 is evaluated using the metrics of lines of code and programming time showing an average of 15x improvement over hand-written VHDL.

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

“…Peripherals are instantiated at the System level as shown in Figure 4; relevant parameters identify the name of the instantiated peripheral, the number of LSU ports required and secondary channel arbitration. As it stands, the micro-architecture fully supports the accelerators designed with ROCCC 2.0 [29]. The close integration of pipelined accelerators to the processor core is a key characteristic of this design and a differentiator to the previous LE1 effort.…”

Embedded Implementation of VHR Satellite Image Segmentation

“…design usually requires about 300 K lines register-transfer level code, while the code density can be easily reduced by 7 − 10× when moved to high-level specification in C-like languages, resulting in a much reduced design complexity. Villarreal et al [31] present a Riverside Optimizing Compiler for Configurable Circuits (ROCCC) that achieves an average improvement of 15% in terms of the metrics of lines of code and programming time over hand-written VHDL in evaluation experiments. Consequently, we first propose a design flow and its tool kits, which incorporate the high-level synthesis technique for its advantages of high development productivity.…”

Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software

“…Below we present a description of some of the common HLS tools and the optimizations they support. [5] Cadence No DK Design Suite [31] Mentor Graphics No GAUT [17] b U. Bretagne -c MaxCompiler [29] Maxeler No ROCCC [39] Jacquard Comp. No Synphony C [37] Synopsys No CyberWorkBench [34] NEC No VivadoHLS [44] Xilinx Yes Intel HLS Compiler [25] Intel Corp.…”