Hardware architectures for the Tate pairing over GF(2m)

A Comparison between Hardware Accelerators for the Modified Tate Pairing over $\mathbb{F}_{2^m}$ and $\mathbb{F}_{3^m}$

“…General purpose microprocessors are intrinsically not suited for computations on finite fields of small characteristic, hence software implementations are bound to be quite slow and the need for special purpose hardware coprocessors is strong [4,5,10,15,17,19,20,[28][29][30]33]. In this context, we extend here to the characteristic two the results by Beuchat et al [4] in the case of the hardware implementation of the reduced η T pairing in characteristic three.…”

“…Finally, we explored the trade-offs involved in the hardware implementation of the modified Tate pairing for both characteristic two and three. Our architectures are based on the unified arithmetic operator introduced in [3], and achieve a better area-time trade-off compared to previously published solutions [10,15,17,19,20,[28][29][30]33].…”

Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers

“…To our knowledge, the place-and-route results on several Xilinx FPGA devices of our designs improved both the computation time and the area-time tradeoff of all the hardware pairing coprocessors previously published in the open literature [28,29,1,30,19,32,41,40,39,7,43,10,25]. We are also currently applying the same methodology used in this work to design a coprocessor for the Tate pairing over F 2 m , with promising preliminary results.…”

A low-power pairing-based cryptographic accelerator for embedded security applications

“…In this paper we report on a low-power ASIC implementation of a dual-mode Tate pairing/point-scalar multiplication processor, due to Keller et al [3]. Their paper describes two pairing processor architectures, each targeted at different applications.…”