Hardware Architecture for the Regular Interpolation Filter of the AV1 Video Coding Standard

Freitas, Daiane; Silva, Rafael da; Siqueira, Ícaro; Diniz, Cláudio M.; Reis, Ricardo; Grellert, Mateus

doi:10.23919/eusipco47968.2020.9287551

Cited by 8 publications

(17 citation statements)

References 13 publications

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“…Domanski et al [57] and Freitas et al [58] presented architectures for the subpixel interpolation filter present in the inter prediction module of the decoder. In [57], the samplelevel parallelism of the architecture allows the processing of any block size as subblocks of size 4×4 (16 samples per cycle), but since it is a decoder design, only one of the many supported filters is used per predicted block (the one signaled in the bitstream).…”

Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 99%

“…The authors reported a throughput of UHD 8K at 30 fps. In [58], the level of parallelism is configurable, ranging from 4 to 128 samples per cycle. Because of this, the authors reported a throughput of UHD 8K at 120 fps, which is much higher than what was achieved by [57], but at the cost of a higher gate count and power dissipation.…”

Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 99%

See 1 more Smart Citation

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

Corrêa

Saldanha

Borges

et al. 2021

IEEE Open J. Circuits Syst.

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This article presents an extensive review of the state-of-the-art system-level solutions featuring complexity reduction and/or dedicated hardware designs for the AV1 and VVC video coding formats. These formats introduced several novel coding techniques compared to their predecessors to improve the coding efficiency at the cost of a significant computational cost. In this article, we discuss the main novelties of AV1 and VVC in each coding module, including block partitioning, intra and inter prediction, transform, entropy coding, and in-loop filters. Then, we present the main published works focusing on complexity reduction and hardware designs for AV1 and VVC. Most of the complexity reduction solutions target the complex and flexible block partitioning structures of these encoders to provide a better tradeoff between coding efficiency and complexity reduction whereas the hardware designs focus on the challenge of implementing the new coding tools to attend real-time processing of high-definition videos. Even with the presented works reaching impressive results, these research fields remain opened for innovative contributions, as discussed in this article.

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Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 99%

Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 99%

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

Corrêa

Saldanha

Borges

et al. 2021

IEEE Open J. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…A few works in the literature present hardware designs for AV1 inter prediction. In [39], the authors present a hardware for the MC interpolation filters, whereas in [13] and [40] the authors focus on the AV1 FME interpolation filters.…”

Section: Inter-frame Predictionmentioning

confidence: 99%

“…In addition, novel and complex modes are tested, such as the Affine/Warped mode in VVC and AV1. Works targeting dedicated hardware designs for the inter prediction explore several techniques to obtain gains in coding efficiency, energy consumption, required area, high throughput and memory bandwidth, such as: multiplierless implementations [11], [12], [13], [37], [39], [40], [38]; approximate computing solutions [37], [13], [42]; reuse of common subexpression [11], [39], [12]; parallelism exploration [11], [37], [39], [40]; and hardware reconfigurability [41].…”

Section: Inter-frame Predictionmentioning

confidence: 99%

Modern Video Coding: Methods, Challenges and Systems

Palau

Silveira

Domanski

et al. 2021

JICS

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With the increasing demand for digital video applications in our daily lives, video coding and decoding become critical tasks that must be supported by several types of devices and systems. This paper presents a discussion of the main challenges to design dedicated hardware architectures based on modern hybrid video coding formats, such as the High Efficiency Video Coding (HEVC), the AOMedia Video 1 (AV1) and the Versatile Video Coding (VVC). The paper discusses eachstep of the hybrid video coding process, highlighting the main challenges for each codec and discussing the main hardware solutions published in the literature. The discussions presented in the paper show that there are still many challenges to be overcome and open research opportunities, especially for the AV1 and VVC codecs. Most of these challenges are related to the high throughput required for processing high and ultrahigh resolution videos in real time and to energy constraints of multimedia-capable devices.

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“…Other works in the literature also proposed hardware architectures for interpolation tools, however without the use of approximate computing, like [21], [22], [23], [24]. Some of these works target other video standards rather than AV1, and some are targeting other video coding tools that also require interpolation filters, like the MC.…”

Section: Introductionmentioning

confidence: 99%

Ultra-High Definition AV1 FME Interpolation Architectures Exploring Approximate Computing

Kolodziejski

Domanski

Porto

et al. 2022

JICS

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Modern video encoders like the AOMedia Video 1 (AV1) implement several complex tools to allow the required high level of compression efficiency. The Fractional Motion Estimation (FME) is one of these complex tools, and AV1 FME defines 42 different interpolation filters. To handle such complexity, hardware acceleration using approximate computing has become an interesting alternative to be explored. This paper presents three optimized approximate architectures for the AV1 FME interpolation filters. The architectures reach real time interpolation for UHD 4K videos at 30 frames per second in a low cost, low power, and memory-efficient design. The architectures were synthesized for a 40nm TSMC standard-cells technology reaching power gains up to 83%, when compared to a precise architecture, and up to 20% when compared to a previously published approximated solution. The area gains were also expressive: up to 83% and 40%, respectively. The architectures also allow a memory bandwidth reduction of up to 59.5%, in comparison with the state-of-the-art solutions. The approximations implied small coding efficiency degradation of 0.54% and 1.25% in BD-BR. The presented architectures have the best results found in the literature when considering the trade-off among hardware cost, power dissipation, processing rate, memory bandwidth, and coding efficiency.

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Hardware Architecture for the Regular Interpolation Filter of the AV1 Video Coding Standard

Cited by 8 publications

References 13 publications

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

Modern Video Coding: Methods, Challenges and Systems

Ultra-High Definition AV1 FME Interpolation Architectures Exploring Approximate Computing

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